12位250MSPS流水線ADC關鍵設計技術研究
發(fā)布時間：2018-10-17 09:21
【摘要】：現(xiàn)代集成電路中,模數(shù)轉換器(ADC)是將現(xiàn)實世界的模擬信號轉換為數(shù)字信號系統(tǒng)可以處理的形式的基礎模塊。隨著CMOS工藝的持續(xù)縮減,增長的器件截止頻率與更小的寄生電容使得數(shù)字電路可以實現(xiàn)更節(jié)能、更快速地邏輯電路,也使得在一個芯片上實現(xiàn)更復雜、更大的系統(tǒng)成為了可能。然而,同樣隨工藝發(fā)展而改變的器件參數(shù),例如更低的本征輸出電阻,更低的供電電壓,更大的漏電流以及更加多變的器件特性,成為模擬電路設計最大的挑戰(zhàn)。簡而言之,越是先進的工藝,器件的本征增益也就越低。因此,高性能的轉換器的設計也面臨全新的挑戰(zhàn)。在各種不同類型的ADC中,流水線ADC是一種可以很好地折衷速度、精度、面積和功耗等重要性能參數(shù)的模數(shù)轉換器。因此被廣泛地應用于高速的無線通信電子系統(tǒng)中。本文首先對流水線ADC的系統(tǒng)結構、電路原理進行了分析與研究。冗余校準算法是流水線ADC電路結構的基礎,使采用若干低量化位數(shù)的流水線級來構成高量化位數(shù)的ADC成為可能。然后,對運放的開關電容電路是如何實現(xiàn)MDAC電路中S/H電路、Sub-DAC、減法器、放大器等模塊的功能進行原理介紹與實例分析。其次分析了MDAC電路的位數(shù)與電路的各性能參數(shù)之間的關系,并綜合考慮后,做出電路結構的最優(yōu)選擇。針對本文選用的SHA-less結構中所存在的時鐘偏差問題也進行了簡要的分析與討論,給出了時鐘偏差的校準思路與方法。基于TSMC 65nm CMOS技術,本文設計實現(xiàn)了一款分辨率為12 bit、采樣速率為250MS/s的流水線ADC。分析了電路設計過程中參數(shù)的計算,功能的實現(xiàn),主要是對流水線ADC中的關鍵電路MDAC的實現(xiàn),并對其工作過程進行了詳細地公式推導。第一級MDAC中所采用的運放也進行了詳細地原理分析,以及性能提升技術的學習,選定了最終的結構并進行了認真的計算推導、仿真驗證,調整再仿真,最終達到了相當水平的性能。第四章中就第三章中所設計的電路進行了系統(tǒng)的仿真,給出了運放模塊、第一級MDAC模塊以及整體流水線ADC電路的仿真驗證,結果表明,達到了設計的目的。電路的電源電壓為2.5V,輸入電壓范圍-1~+1V,時鐘頻率為250MS/s。仿真結果表明,輸入的差分正弦信號頻率為10.7MHz時,第一級輸出有效位數(shù)達到14.87 bit,無雜散動態(tài)范圍(SFDR)為98.6 dB,信噪失真比(SNDR)為91.3 dB。同時,整體ADC的ENOB為11.96 bit,SFDR和SNDR分別為86.7 dB和73.7 dB。當輸入信號頻率為108MHz時,第一級MDAC的ENOB為13.89 bit,SFDR和SNDR分別為90.3 dB和85.38 dB,整體電路有效位數(shù)為11.81 bit,SFDR和SNDR分別為81.9dB和72.86 dB。仿真結果表明,本設計能滿足設計的目標。同時在中頻(IF)采樣時,依然有足夠的電路特性。
[Abstract]:In modern integrated circuits, the analog-to-digital converter (ADC) is a basic module that converts real world analog signals into digital signal systems. As the CMOS process continues to shrink, increasing device cutoff frequencies and smaller parasitic capacitors make it possible for digital circuits to achieve more energy efficient, faster logic circuits and more complex, larger systems on a single chip. However, the device parameters, such as lower intrinsic output resistance, lower supply voltage, larger leakage current and more variable device characteristics, are the biggest challenges in analog circuit design. In short, the more advanced the process, the lower the intrinsic gain of the device. Therefore, the design of high-performance converters also faces new challenges. Among different types of ADC, pipelined ADC is an analog-to-digital converter that can compromise the important performance parameters such as speed, precision, area and power consumption. Therefore, it is widely used in high-speed wireless communication electronic systems. Firstly, the system structure and circuit principle of pipelined ADC are analyzed and studied in this paper. Redundant calibration algorithm is the basis of pipelined ADC circuit structure, which makes it possible to use pipeline of low quantization bits to construct ADC with high quantization bit. Then, how to realize the function of S / H circuit, Sub-DAC, subtractor, amplifier and so on in MDAC circuit is introduced and an example is given. Secondly, the relationship between the bit number of MDAC circuit and the performance parameters of the circuit is analyzed, and the optimal selection of the circuit structure is made after comprehensive consideration. This paper also briefly analyzes and discusses the clock deviation problem in the SHA-less structure selected in this paper, and gives the calibration thought and method of the clock deviation. Based on TSMC 65nm CMOS technology, a pipelined ADC. with a resolution of 12 bit, sampling rate of 250MS/s is designed and implemented in this paper. In this paper, the calculation of parameters and the realization of function in circuit design are analyzed. The key circuit MDAC in pipelined ADC is mainly realized, and its working process is deduced in detail. The operational amplifier used in the first stage MDAC is also analyzed in detail, and the learning of the performance improvement technology is also carried out. Finally, the final structure is selected, and the calculation, deduction, simulation verification, adjustment and resimulation are carried out. Finally, the performance is quite high. In the fourth chapter, the circuit designed in chapter 3 is simulated systematically, and the simulation verification of the operational amplifier module, the first stage MDAC module and the whole pipeline ADC circuit is given. The result shows that the purpose of the design is achieved. The supply voltage of the circuit is 2.5 V, the input voltage range is -1 ~ 1 V, and the clock frequency is 250 Ms / s. The simulation results show that when the input frequency of the differential sinusoidal signal is 10.7MHz, the effective bit number of the first stage output reaches 14.87 bit, (SFDR) is 98.6 dB, the signal-noise-to-noise ratio (SNDR) is 91.3 dB.. Meanwhile, the ENOB of the whole ADC is 11.96 bit,SFDR and the SNDR is 86.7 dB and 73.7 dB., respectively. When the input signal frequency is 108MHz, the ENOB of the first stage MDAC is 13.89 bit,SFDR and the SNDR is 90.3 dB and 85.38 dB,. The effective bits of the whole circuit are 11.81 bit,SFDR and 72.86 dB., respectively. Simulation results show that the design can meet the design objectives. At the same time, if (IF) sampling, there are still enough circuit characteristics.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN792
[Abstract]:In modern integrated circuits, the analog-to-digital converter (ADC) is a basic module that converts real world analog signals into digital signal systems. As the CMOS process continues to shrink, increasing device cutoff frequencies and smaller parasitic capacitors make it possible for digital circuits to achieve more energy efficient, faster logic circuits and more complex, larger systems on a single chip. However, the device parameters, such as lower intrinsic output resistance, lower supply voltage, larger leakage current and more variable device characteristics, are the biggest challenges in analog circuit design. In short, the more advanced the process, the lower the intrinsic gain of the device. Therefore, the design of high-performance converters also faces new challenges. Among different types of ADC, pipelined ADC is an analog-to-digital converter that can compromise the important performance parameters such as speed, precision, area and power consumption. Therefore, it is widely used in high-speed wireless communication electronic systems. Firstly, the system structure and circuit principle of pipelined ADC are analyzed and studied in this paper. Redundant calibration algorithm is the basis of pipelined ADC circuit structure, which makes it possible to use pipeline of low quantization bits to construct ADC with high quantization bit. Then, how to realize the function of S / H circuit, Sub-DAC, subtractor, amplifier and so on in MDAC circuit is introduced and an example is given. Secondly, the relationship between the bit number of MDAC circuit and the performance parameters of the circuit is analyzed, and the optimal selection of the circuit structure is made after comprehensive consideration. This paper also briefly analyzes and discusses the clock deviation problem in the SHA-less structure selected in this paper, and gives the calibration thought and method of the clock deviation. Based on TSMC 65nm CMOS technology, a pipelined ADC. with a resolution of 12 bit, sampling rate of 250MS/s is designed and implemented in this paper. In this paper, the calculation of parameters and the realization of function in circuit design are analyzed. The key circuit MDAC in pipelined ADC is mainly realized, and its working process is deduced in detail. The operational amplifier used in the first stage MDAC is also analyzed in detail, and the learning of the performance improvement technology is also carried out. Finally, the final structure is selected, and the calculation, deduction, simulation verification, adjustment and resimulation are carried out. Finally, the performance is quite high. In the fourth chapter, the circuit designed in chapter 3 is simulated systematically, and the simulation verification of the operational amplifier module, the first stage MDAC module and the whole pipeline ADC circuit is given. The result shows that the purpose of the design is achieved. The supply voltage of the circuit is 2.5 V, the input voltage range is -1 ~ 1 V, and the clock frequency is 250 Ms / s. The simulation results show that when the input frequency of the differential sinusoidal signal is 10.7MHz, the effective bit number of the first stage output reaches 14.87 bit, (SFDR) is 98.6 dB, the signal-noise-to-noise ratio (SNDR) is 91.3 dB.. Meanwhile, the ENOB of the whole ADC is 11.96 bit,SFDR and the SNDR is 86.7 dB and 73.7 dB., respectively. When the input signal frequency is 108MHz, the ENOB of the first stage MDAC is 13.89 bit,SFDR and the SNDR is 90.3 dB and 85.38 dB,. The effective bits of the whole circuit are 11.81 bit,SFDR and 72.86 dB., respectively. Simulation results show that the design can meet the design objectives. At the same time, if (IF) sampling, there are still enough circuit characteristics.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN792
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