發(fā)布時(shí)間：2018-10-13 10:35

【摘要】：現(xiàn)今集成電路的發(fā)展也伴隨著移動(dòng)互聯(lián)網(wǎng)的發(fā)展以及手持設(shè)備的廣泛運(yùn)用,集成電路的功耗變成除時(shí)鐘頻率以及面積外又一個(gè)值得關(guān)注的問題。而低功耗技術(shù)則變成了集成電路設(shè)計(jì)中值得研究的課題。本文分析了CMOS電路功耗的主要組成,其組成主要分為靜態(tài)功耗以及動(dòng)態(tài)功耗。并且按照芯片設(shè)計(jì)的不同階段研究了目前常用的低功耗設(shè)計(jì)方法,主要設(shè)計(jì)階段包括系統(tǒng)設(shè)計(jì)、電路設(shè)計(jì)、電路綜合以及設(shè)計(jì)實(shí)現(xiàn)過程中。數(shù)字電路的低功耗設(shè)計(jì)是貫穿于芯片設(shè)計(jì)的整個(gè)階段。目前常用的低功耗設(shè)計(jì)方法有門控時(shí)鐘、多閾值電壓、電源關(guān)掉、多電源供電技術(shù)等。同時(shí)本文以武漢芯泰公司基帶處理芯片BB為研究對(duì)象,后端設(shè)計(jì)采用的工藝為SMIC130nm G,主要在電路綜合以及版圖設(shè)計(jì)階段實(shí)現(xiàn)低功耗設(shè)計(jì)。并針對(duì)該芯片,本文按照設(shè)計(jì)階段的不同,首先在電路綜合階段研究了結(jié)點(diǎn)電容優(yōu)化、多閾值電壓技術(shù)、操作數(shù)隔離技術(shù)、門控時(shí)鐘技術(shù)對(duì)電路動(dòng)態(tài)功耗以及靜態(tài)功耗優(yōu)化的程度。同時(shí)在版圖設(shè)計(jì)階段著重研究了使用UPF/CPF電源約束對(duì)基帶處理芯片BB進(jìn)行電源關(guān)掉設(shè)計(jì)以及時(shí)鐘樹綜合低功耗實(shí)現(xiàn)。經(jīng)過多方面的實(shí)驗(yàn),結(jié)點(diǎn)電容技術(shù)對(duì)功耗的優(yōu)化能達(dá)到2%、多閾值電壓設(shè)計(jì)對(duì)功耗的優(yōu)化能達(dá)到28%、操作數(shù)隔離技術(shù)在多組合電路中的功耗優(yōu)化能達(dá)到15%、門控時(shí)鐘技術(shù)在多時(shí)序電路中優(yōu)化能達(dá)到70%、低功耗時(shí)鐘樹技術(shù)對(duì)時(shí)鐘樹的功耗優(yōu)化能達(dá)到50%
[Abstract]:With the development of mobile Internet and the wide use of handheld devices, the power consumption of integrated circuits has become a problem worth paying attention to besides clock frequency and area. Low-power technology has become a subject worth studying in integrated circuit design. In this paper, the main components of CMOS circuit power consumption are analyzed, including static power consumption and dynamic power consumption. And according to the different stages of chip design, the commonly used low-power design methods are studied. The main design stages include system design, circuit synthesis and the process of design and implementation. The low power design of digital circuit runs through the whole stage of chip design. The commonly used low-power design methods include gated clock, multi-threshold voltage, power off, multi-power supply technology and so on. At the same time, this paper takes the baseband processing chip BB of Wuhan Xintai Company as the research object. The back-end design process is SMIC130nm G, which mainly realizes the low-power design in the stage of circuit synthesis and layout design. According to the different design stages, this paper first studies the node capacitance optimization, multi-threshold voltage technology, Operand isolation technology in the circuit synthesis stage. The degree to which the gated clock technology optimizes the dynamic and static power consumption of the circuit. At the same time, in the layout design phase, the power off design of baseband processing chip BB using UPF/CPF power constraints and the implementation of clock tree synthesis with low power consumption are studied. After many experiments, Node capacitance technology can optimize power consumption by 2 steps, multi-threshold voltage design can optimize power consumption by 28 steps, Operand isolation technology can achieve 15 steps in multi-combinational circuits, and gated clock technology can be used to optimize power consumption in multi-sequential circuits. The conversion energy can reach 70%, and the low power clock tree technology can optimize the power consumption of the clock tree by 50%.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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本文編號(hào)：2268307