新型低阻通道三維橫向MOS研究
發(fā)布時間：2018-10-13 09:09
【摘要】：橫向功率MOSFET存在比導通電阻與擊穿電壓的折中關系,常見的改善方法有RESURF(Reduced surface field)技術和超結(Super Junction,SJ)技術,這兩種技術皆通過增強耗盡來提高漂移區(qū)摻雜濃度。本文提出新的電流輸運模式,構建多數(shù)載流子積累層,由積累層形成的低阻通道和中性漂移區(qū)共同傳輸電流,顯著降低器件的導通電阻,打破了橫向MOSFET的“硅極限”。本文提出兩類新型的具有連續(xù)低阻通道的橫向超結LDMOS。(1)具有槽型增強積累延伸柵(Enhanced-accumulation trench-type extending gate,TEG)的超結LDMOS(TEG SJ LDMOS),該結構的特征在于嵌入漂移區(qū)中的槽型增強積累延伸柵,TEG由高k介質及P柱區(qū)構成。槽型增強積累延伸柵有兩個作用:一是正向導通時,在高k介質與N柱區(qū)界面形成多數(shù)載流子積累層,且高k介質增強電荷積累作用,多數(shù)載流子積累層聯(lián)合溝道構成從源至漏的連續(xù)低阻通道,有效降低比導通電阻;二是高k介質輔助耗盡漂移區(qū),調制器件體內(nèi)電場。仿真表明,TEG SJ LDMOS耐壓為197V,比導通電阻為1.09 mΩ?cm2。針對襯底輔助耗盡效應,提出兩種柱區(qū)階梯摻雜的TEG SJ LDMOS。一是N柱區(qū)階梯摻雜TEG SJ LDMOS,階梯摻雜的N柱區(qū)有效抑制襯底輔助耗盡效應且調制器件表面電場,耐壓從197V提升至217V。二是P柱區(qū)階梯摻雜TEG SJ LDMOS,P柱區(qū)在漏端采用輕摻雜P1區(qū),P1區(qū)減少了襯底輔助耗盡引起的P型雜質過剩,保持超結區(qū)的電荷平衡,器件獲得耐壓218V。(2)具有輔助積累延伸柵(Assisted-accumulation extending gate,AEG)的SJ LDMOS。這類器件的主要特征是位于器件表面的輔助積累延伸柵,開態(tài)時,N柱區(qū)表面形成電子積累層,P柱區(qū)表面形成電子反型層,積累層與反型層聯(lián)合溝道構成從源至漏的連續(xù)低阻通道,低阻通道顯著降低器件比導通電阻。為改善SJ LDMOS的耐壓,提出具有階梯摻雜N型緩沖層的AEG SJ LDMOS(AEG-SNB SJ LDMOS)及具有P型埋層的AEG SJ LDMOS(AEG-PB SJ LDMOS)。階梯摻雜N-buffer在源端和漏端提供非均勻的電荷補償,有效抑制襯底輔助耗盡效應。通過仿真,AEG-SNB SJ LDMOS得到235V的耐壓及2.92mΩ?cm2的比導通電阻。P型埋層減少源端過剩的補償電荷,并調制器件表面電場。仿真表明,AEG-PB SJ LDMOS獲得220V的耐壓及3.05 mΩ?cm2的比導通電阻。
[Abstract]:Transverse power MOSFET has a trade-off between specific on-resistance and breakdown voltage. Common improvement methods include RESURF (Reduced surface field) technique and overjunction (Super Junction,SJ) technique, both of which increase the doping concentration in drift region by enhanced depletion. In this paper, a new current transport mode is proposed to construct the majority carrier accumulation layer. The low resistance channel and neutral drift region formed by the accumulation layer can significantly reduce the on-resistance of the device and break the "silicon limit" of the transverse MOSFET. In this paper, we present two new types of transversely superjunction LDMOS. (1) with grooved enhanced accumulative extension gate (Enhanced-accumulation trench-type extending gate,TEG) with continuous low resistance channels. The structure is characterized by embedded grooves in the drift region. TEG is composed of a slotted enhanced accumulative extended gate (TEG). High k medium and P column region. The groove-type enhanced accumulation extension gate has two functions: one is the formation of a majority carrier accumulation layer at the interface between the high k medium and the N column, and the enhancement of charge accumulation in the high k medium. The continuous low resistance channel from source to drain is formed by the combination of most carrier accumulative layer and channel, which can effectively reduce the specific on-resistance; second, the high k dielectric auxiliary depletion drift region and the internal electric field of the modulator. The simulation results show that the, TEG SJ LDMOS voltage is 197V and the specific on-resistance is 1.09 m 惟? cm2.. In this paper, two kinds of pillared step doped TEG SJ LDMOS. are proposed for substrate assisted depletion effect. The first is that the N-column region doped with TEG SJ LDMOS, step in the N column region can effectively suppress the substrate assisted depletion effect and the electric field on the surface of the modulator, and the withstand voltage is raised from 197V to 217V. On the other hand, the step doped TEG SJ LDMOS,P column in P column region adopts light doping P1 region at the leakage end, which reduces the excess P-type impurity caused by substrate assisted depletion and keeps the charge balance in the superjunction region. (2) SJ LDMOS. with auxiliary accumulative extension gate (Assisted-accumulation extending gate,AEG). The main characteristic of this kind of devices is that the auxiliary accumulative extension gate is located on the surface of the device. In the open state, the electron accumulation layer is formed on the N column surface and the electron inversion layer is formed on the P column surface. The accumulation layer and the inversion layer combine the channel to form the continuous low resistance channel from the source to the drain, and the low resistance channel reduces the specific on-resistance of the device significantly. In order to improve the voltage resistance of SJ LDMOS, AEG SJ LDMOS (AEG-SNB SJ LDMOS) with step doped N-type buffer layer and AEG SJ LDMOS (AEG-PB SJ LDMOS). With P-type buried layer were proposed. Step doped N-buffer provides nonuniform charge compensation at the source and drain ends, which effectively inhibits the substrate-assisted depletion effect. The simulation results show that the voltage of 235V and the specific on-resistance of 2.92m 惟? cm2 are obtained by AEG-SNB SJ LDMOS. The P-type burying layer reduces the excess compensation charge at the source end and modulates the surface electric field of the device. The simulation results show that the AEG-PB SJ LDMOS has a voltage of 220 V and a specific on-resistance of 3.05 m 惟? cm2.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386
本文編號：2268048
[Abstract]:Transverse power MOSFET has a trade-off between specific on-resistance and breakdown voltage. Common improvement methods include RESURF (Reduced surface field) technique and overjunction (Super Junction,SJ) technique, both of which increase the doping concentration in drift region by enhanced depletion. In this paper, a new current transport mode is proposed to construct the majority carrier accumulation layer. The low resistance channel and neutral drift region formed by the accumulation layer can significantly reduce the on-resistance of the device and break the "silicon limit" of the transverse MOSFET. In this paper, we present two new types of transversely superjunction LDMOS. (1) with grooved enhanced accumulative extension gate (Enhanced-accumulation trench-type extending gate,TEG) with continuous low resistance channels. The structure is characterized by embedded grooves in the drift region. TEG is composed of a slotted enhanced accumulative extended gate (TEG). High k medium and P column region. The groove-type enhanced accumulation extension gate has two functions: one is the formation of a majority carrier accumulation layer at the interface between the high k medium and the N column, and the enhancement of charge accumulation in the high k medium. The continuous low resistance channel from source to drain is formed by the combination of most carrier accumulative layer and channel, which can effectively reduce the specific on-resistance; second, the high k dielectric auxiliary depletion drift region and the internal electric field of the modulator. The simulation results show that the, TEG SJ LDMOS voltage is 197V and the specific on-resistance is 1.09 m 惟? cm2.. In this paper, two kinds of pillared step doped TEG SJ LDMOS. are proposed for substrate assisted depletion effect. The first is that the N-column region doped with TEG SJ LDMOS, step in the N column region can effectively suppress the substrate assisted depletion effect and the electric field on the surface of the modulator, and the withstand voltage is raised from 197V to 217V. On the other hand, the step doped TEG SJ LDMOS,P column in P column region adopts light doping P1 region at the leakage end, which reduces the excess P-type impurity caused by substrate assisted depletion and keeps the charge balance in the superjunction region. (2) SJ LDMOS. with auxiliary accumulative extension gate (Assisted-accumulation extending gate,AEG). The main characteristic of this kind of devices is that the auxiliary accumulative extension gate is located on the surface of the device. In the open state, the electron accumulation layer is formed on the N column surface and the electron inversion layer is formed on the P column surface. The accumulation layer and the inversion layer combine the channel to form the continuous low resistance channel from the source to the drain, and the low resistance channel reduces the specific on-resistance of the device significantly. In order to improve the voltage resistance of SJ LDMOS, AEG SJ LDMOS (AEG-SNB SJ LDMOS) with step doped N-type buffer layer and AEG SJ LDMOS (AEG-PB SJ LDMOS). With P-type buried layer were proposed. Step doped N-buffer provides nonuniform charge compensation at the source and drain ends, which effectively inhibits the substrate-assisted depletion effect. The simulation results show that the voltage of 235V and the specific on-resistance of 2.92m 惟? cm2 are obtained by AEG-SNB SJ LDMOS. The P-type burying layer reduces the excess compensation charge at the source end and modulates the surface electric field of the device. The simulation results show that the AEG-PB SJ LDMOS has a voltage of 220 V and a specific on-resistance of 3.05 m 惟? cm2.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386
【相似文獻】
相關碩士學位論文 前1條
1 田瑞超;新型低阻通道三維橫向MOS研究[D];電子科技大學;2015年
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