基于支持向量機(jī)的濾波器設(shè)計(jì)及硬件實(shí)現(xiàn)
發(fā)布時(shí)間：2018-10-10 11:49
【摘要】：濾波器是電子設(shè)備中的常見(jiàn)模塊,經(jīng)典的濾波器設(shè)計(jì)方法有窗函數(shù)法,頻率抽取法等。自機(jī)器學(xué)習(xí)的理論出現(xiàn)后,神經(jīng)網(wǎng)絡(luò)等算法廣泛應(yīng)用到FIR濾波器的設(shè)計(jì)中。本文針對(duì)傳統(tǒng)FIR濾波器設(shè)計(jì)方法及神經(jīng)網(wǎng)絡(luò)設(shè)計(jì)方法的不足,在改進(jìn)使用支持向量機(jī)(SVM)設(shè)計(jì)FIR濾波器方法的基礎(chǔ)上,提出了 SVM設(shè)計(jì)FIR濾波器的硬件實(shí)現(xiàn)方法,將由SVM設(shè)計(jì)的濾波器移植到硬件上。使用SVM構(gòu)造FIR濾波器,得到的濾波器可更新,并且使用的訓(xùn)練樣本較少,本文中使用理想濾波器的幅值響應(yīng)訓(xùn)練SVM。在建立SVM模型的過(guò)程中,本文引入針對(duì)訓(xùn)練集輸出值的放大參數(shù),該參數(shù)將數(shù)據(jù)集分離,并影響最終的幅頻響應(yīng)。SVM模型中訓(xùn)練參數(shù)較多,如訓(xùn)練組數(shù)、懲罰參數(shù)、核函數(shù)參數(shù)等,本文進(jìn)行多次測(cè)試,將結(jié)果進(jìn)行比較得到最優(yōu)訓(xùn)練參數(shù),據(jù)此構(gòu)建基于SVM的FIR濾波器模型。相對(duì)于窗函數(shù),使用S VM設(shè)計(jì)的濾波器具有良好的幅頻特性,邊界控制較為精確,通帶較為平緩,阻帶波動(dòng)次數(shù)較少,衰減較多。為了保證濾波器的可更改性和便于其移植到其他系統(tǒng)里,利用生成的FIR濾波器模型構(gòu)建一個(gè)位于FPGA上的嵌入式系統(tǒng)。FIR濾波器嵌入式系統(tǒng)主要由SVM構(gòu)成,對(duì)SVM算法中頻繁出現(xiàn)的核函數(shù)計(jì)算以及浮點(diǎn)數(shù)乘法加法運(yùn)算進(jìn)行硬件實(shí)現(xiàn),對(duì)SVM算法中的訓(xùn)練部分和分類部分進(jìn)行軟件框架實(shí)現(xiàn)。本文對(duì)核函數(shù)的硬件實(shí)現(xiàn)進(jìn)行優(yōu)化,針對(duì)RBF核函數(shù),進(jìn)行算法上的改進(jìn),加速運(yùn)算,同時(shí)使用流水線、向量分割等方法加速硬件系統(tǒng),并平衡速度與資源。最終系統(tǒng)中單次分類測(cè)試向量的時(shí)間約為20us,濾波準(zhǔn)確率可達(dá)到98.41%。
[Abstract]:Filter is a common module in electronic equipment. The classical filter design methods include window function method, frequency decimation method and so on. Since the emergence of the theory of machine learning, neural networks and other algorithms are widely used in the design of FIR filters. Aiming at the shortcomings of the traditional FIR filter design method and the neural network design method, this paper proposes a hardware implementation method of SVM design FIR filter based on improving the FIR filter design method using support vector machine (SVM). The filter designed by SVM is transplanted to hardware. Using SVM to construct FIR filter, the filter can be updated and less training samples are used. In this paper, the amplitude response of ideal filter is used to train SVM.. In the process of establishing the SVM model, this paper introduces the amplification parameter for the output value of the training set, which separates the data set and affects the final amplitude-frequency response. There are many training parameters in the SVM model, such as the number of training groups and the penalty parameter. The kernel function parameters are tested several times in this paper, and the optimal training parameters are obtained by comparing the results, and then the FIR filter model based on SVM is constructed. Compared with the window function, the filter designed by S VM has good amplitude-frequency characteristic, the boundary control is more accurate, the passband is more gentle, the frequency of stopband fluctuation is less, and the attenuation is more. In order to ensure the modifiability of the filter and to transplant it to other systems, an embedded system. Fir filter embedded system based on FPGA is constructed by using the generated FIR filter model. The embedded system is mainly composed of SVM. The kernel function calculation and floating-point multiplication addition in SVM algorithm are implemented by hardware, and the training part and classification part of SVM algorithm are implemented by software framework. In this paper, the hardware implementation of kernel function is optimized. For RBF kernel function, the algorithm is improved and the operation is accelerated. At the same time, pipeline and vector partition are used to accelerate the hardware system, and the speed and resources are balanced. In the final system, the time of single classification test vector is about 20us, and the filtering accuracy can reach 98.41%.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN713
本文編號(hào)：2261651
[Abstract]:Filter is a common module in electronic equipment. The classical filter design methods include window function method, frequency decimation method and so on. Since the emergence of the theory of machine learning, neural networks and other algorithms are widely used in the design of FIR filters. Aiming at the shortcomings of the traditional FIR filter design method and the neural network design method, this paper proposes a hardware implementation method of SVM design FIR filter based on improving the FIR filter design method using support vector machine (SVM). The filter designed by SVM is transplanted to hardware. Using SVM to construct FIR filter, the filter can be updated and less training samples are used. In this paper, the amplitude response of ideal filter is used to train SVM.. In the process of establishing the SVM model, this paper introduces the amplification parameter for the output value of the training set, which separates the data set and affects the final amplitude-frequency response. There are many training parameters in the SVM model, such as the number of training groups and the penalty parameter. The kernel function parameters are tested several times in this paper, and the optimal training parameters are obtained by comparing the results, and then the FIR filter model based on SVM is constructed. Compared with the window function, the filter designed by S VM has good amplitude-frequency characteristic, the boundary control is more accurate, the passband is more gentle, the frequency of stopband fluctuation is less, and the attenuation is more. In order to ensure the modifiability of the filter and to transplant it to other systems, an embedded system. Fir filter embedded system based on FPGA is constructed by using the generated FIR filter model. The embedded system is mainly composed of SVM. The kernel function calculation and floating-point multiplication addition in SVM algorithm are implemented by hardware, and the training part and classification part of SVM algorithm are implemented by software framework. In this paper, the hardware implementation of kernel function is optimized. For RBF kernel function, the algorithm is improved and the operation is accelerated. At the same time, pipeline and vector partition are used to accelerate the hardware system, and the speed and resources are balanced. In the final system, the time of single classification test vector is about 20us, and the filtering accuracy can reach 98.41%.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN713
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