【摘要】：高速ADC在雷達、無線通信、高速數(shù)據(jù)采集等領(lǐng)域有著廣泛的應(yīng)用。作為完成對數(shù)據(jù)采樣、轉(zhuǎn)換工作的核心模塊,ADC與外部控制器之間的數(shù)據(jù)傳輸,以及其性能的提升逐漸成為了芯片開發(fā)者們研究的熱點。SPI接口總線因其具有傳輸速度快、占用信號線少、信號傳輸準確率高、全雙工等優(yōu)點,在數(shù)據(jù)通信中得到了廣泛應(yīng)用。因此,將SPI接口集成在高速ADC芯片中的設(shè)計理念已然成為了當前高速ADC開發(fā)的主流趨勢。本文基于一款折疊插值架構(gòu)的高速ADC,研究并設(shè)計了適用于高速ADC的SPI接口電路,實現(xiàn)了高速ADC與外部控制器的數(shù)據(jù)串行通信,并研究了對高速ADC的多功能配置,包括校準使能、數(shù)據(jù)時鐘DCLK相位選擇、多通道工作斷電控制、編碼測試功能等。通過采用SPI接口電路對ADC的配置方法,節(jié)約了芯片管腳數(shù),可大大減小芯片面積。另外,還研究了通過SPI接口電路對高速ADC中失配誤差進行校準,包括采樣保持電路的失調(diào)失配以及時序產(chǎn)生電路的采樣時間失配。這種手動校準的設(shè)計方法不但校準精度高,而且具有更好的靈活性和可控制性。本文利用Verlilog HDL硬件描述語言完成了 SPI接口電路的RTL級設(shè)計,利用Modelsim仿真軟件對設(shè)計的SPI接口電路進行了功能仿真,驗證了其功能的正確性,并在數(shù)�；旌戏抡嫫脚_CadenceAMS中,對RTL級的SPI接口電路和基于TSMC0.18μm CMOS工藝的誤差校準電路進行級聯(lián)仿真,結(jié)果表明通過SPI接口電路可以實現(xiàn)失配誤差的校準,其中采樣保持電路的ENOB從8.93bits提升至11.03bits,時序產(chǎn)生電路校準后的采樣時序偏差為0.09ps,有效降低了電路的失配誤差,提升了電路性能,從而改善高速ADC的整體性能。接著,對設(shè)計的SPI接口電路進行FPGA硬件實現(xiàn)與驗證。最后,基于TSMC 0.18μm CMOS工藝庫對SPI接口電路進行ASIC實現(xiàn)與驗證,利用Design Compiler綜合工具完成電路綜合,得到綜合后時序分析報告,結(jié)果表明該SPI接口電路時序滿足設(shè)計要求,并對綜合后的電路進行后仿真驗證,然后利用IC Compiler工具實現(xiàn)了 SPI接口電路的自動布局布線,完成版圖設(shè)計。
[Abstract]:High-speed ADC is widely used in radar, wireless communication, high-speed data acquisition and other fields. As the core module of data sampling and conversion, data transmission between ADC and external controllers, as well as the improvement of its performance, has gradually become a research hotspot for chip developers. With the advantages of fewer signal lines, high transmission accuracy and full duplex, SPI interface has been widely used in data communication. Therefore, the design concept of integrating SPI interface into high-speed ADC chip has become the mainstream trend of high-speed ADC development. SPI interface circuit realizes data serial communication between high-speed ADC and external controller, and studies the multi-functional configuration of high-speed ADC, including calibration enablement, data clock DCLK phase selection, multi-channel power-off control, coding and testing functions. In addition, the mismatch error in high-speed ADC is calibrated by SPI interface circuit, including mismatch of sampling and holding circuit and mismatch of sampling time in timing generation circuit. The RTL-level design of SPI interface circuit is completed with Verlilog HDL hardware description language. The function of the designed SPI interface circuit is simulated with Modelsim simulation software. The correctness of the function is verified. The RTL-level SPI interface circuit and the error calibration based on TSMC 0.18um CMOS process are implemented in CadenceAMS. The cascade simulation results show that the mismatch error can be calibrated by the SPI interface circuit. The ENOB of the sample and hold circuit is increased from 8.93 bits to 11.03 bits, and the sampling timing error is 0.09ps after the timing generation circuit is calibrated. The mismatch error of the circuit is effectively reduced and the performance of the circuit is improved. Finally, based on the TSMC 0.18um CMOS process library, the SPI interface circuit is implemented and verified by ASIC, and the circuit synthesis is completed by the Design Compiler synthesis tool. The timing analysis report is obtained after synthesis. The results show that the SPI interface circuit timing meets the design requirements. Then, the integrated circuit is simulated and verified, and the automatic layout and wiring of SPI interface circuit is realized by using IC Compiler.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792

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