一種具有VLD終端結(jié)構(gòu)的600V VDMOS設(shè)計(jì)
發(fā)布時(shí)間：2018-09-10 15:32
【摘要】：VDMOS是新一代功率半導(dǎo)體器件,具有優(yōu)良的電學(xué)特性,如輸入阻抗高、驅(qū)動(dòng)功率小、安全工作區(qū)寬,不僅廣泛應(yīng)用在民用領(lǐng)域,而且在軍用領(lǐng)域也得到了很好的應(yīng)用。VDMOS設(shè)計(jì)分為元胞區(qū)域和終端區(qū)域,終端結(jié)構(gòu)的設(shè)計(jì)通常使用場板/場限環(huán)結(jié)構(gòu)。但是使用場板/場限環(huán)結(jié)構(gòu)會(huì)使得芯片的面積大,生產(chǎn)成本高,性價(jià)比低。VLD(Variable Lateral Doping)的終端結(jié)構(gòu)與場板/場限環(huán)結(jié)構(gòu)相比大大的減小了終端長度,降低了成產(chǎn)成本,提高了性價(jià)比,是新興的、先進(jìn)的終端結(jié)構(gòu)。然而由于國內(nèi)的VDMOS研究起步較晚,制造工藝與技術(shù)相對落后,所以基本沒有VLD終端結(jié)構(gòu)的產(chǎn)品。因而VLD終端產(chǎn)品的研究對于國內(nèi)VLD終端產(chǎn)品以及相關(guān)產(chǎn)品的開發(fā)具有重要意義。本論文在某個(gè)相關(guān)項(xiàng)目的基礎(chǔ)上,分析VLD及相關(guān)終端結(jié)構(gòu)的工作機(jī)理,并設(shè)計(jì)相對應(yīng)的產(chǎn)品。主要的參數(shù)指標(biāo)是:擊穿電壓大于606 V,閾值電壓為2~4 V,通態(tài)壓降小于1 V,導(dǎo)通電阻小于1.25?。本論文的主要目的是提供一種VLD產(chǎn)品的設(shè)計(jì),為后續(xù)的相關(guān)產(chǎn)品開發(fā)提供參照。本論文的主要內(nèi)容如下:1、簡要介紹終端理論,基于項(xiàng)目合作方的工藝平臺(tái),設(shè)計(jì)工藝流程。通過Tsuprem4/Medici軟件對工藝步驟進(jìn)行優(yōu)化,并進(jìn)行VDMOS元胞部分的仿真,使得仿真結(jié)果滿足項(xiàng)目合作方的參數(shù)要求。2、通過Tsuprem4/Medici軟件進(jìn)行VDMOS終端部分的仿真。首先采用場板/場限環(huán)的終端結(jié)構(gòu),并對場板/場限環(huán)結(jié)構(gòu)進(jìn)行優(yōu)化,得到尖峰電場小于2x105 V/cm符合要求的結(jié)果。在場板/場限環(huán)結(jié)構(gòu)基礎(chǔ)上,對終端長度進(jìn)行縮短,設(shè)計(jì)VLD結(jié)構(gòu),仿真得到電場趨于均勻分布、終端長度大大減小的最優(yōu)結(jié)果。3、繪制版圖,進(jìn)行流片試驗(yàn)。目前的流片獲得部分靜態(tài)參數(shù)具體結(jié)果如下:場限環(huán)/場板終端結(jié)構(gòu)基本符合要求,而VLD終端結(jié)構(gòu)的擊穿電壓為100 V~400 V。結(jié)果表明:流片數(shù)據(jù)部分不滿足設(shè)計(jì)要求。
[Abstract]:VDMOS is a new generation of power semiconductor devices with excellent electrical properties, such as high input impedance, low driving power and wide safe working area. The design of VDMOS is divided into cellular region and terminal area. The design of the terminal structure usually uses the field plate / field limiting ring structure. But using the field board / field limiting ring structure will make the chip large area, high production cost, low performance-price ratio. The terminal structure of .VLD (Variable Lateral Doping) greatly reduces the terminal length, reduces the production cost and improves the performance-price ratio compared with the field board / field limiting ring structure. Is a new, advanced terminal structure. However, due to the late start of VDMOS research and the backward manufacturing process and technology in China, there is basically no product with VLD terminal structure. Therefore, the research of VLD terminal products is of great significance to the development of domestic VLD terminal products and related products. On the basis of a related project, this paper analyzes the working mechanism of VLD and related terminal structure, and designs the corresponding products. The main parameters are as follows: breakdown voltage is more than 606 V, threshold voltage is 2V, on-state voltage drop is less than 1 V, and on-resistance is less than 1.25 V. The main purpose of this paper is to provide a VLD product design for the subsequent related product development. The main contents of this paper are as follows: 1, briefly introduces the terminal theory, based on the process platform of the project partner, designs the process flow. The process steps are optimized by Tsuprem4/Medici software, and the simulation of VDMOS cell part is carried out, which makes the simulation results meet the requirements of the parameter of the project partner. Secondly, the simulation of VDMOS terminal part is carried out by Tsuprem4/Medici software. Firstly, the terminal structure of the field plate / field limiting ring is adopted, and the structure of the field plate / field limiting ring is optimized, and the result that the peak electric field is less than 2x105 V/cm is obtained. On the basis of the field plate / field limiting ring structure, the terminal length is shortened and the VLD structure is designed. The simulation results show that the electric field tends to be uniformly distributed and the terminal length is greatly reduced. Finally, the layout is drawn and the flow sheet test is carried out. At present, some static parameters are obtained as follows: the structure of field limiting ring / field plate terminal basically meets the requirements, while the breakdown voltage of VLD terminal structure is 100V / 400V. The results show that the flow sheet data can not meet the design requirements.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386
[Abstract]:VDMOS is a new generation of power semiconductor devices with excellent electrical properties, such as high input impedance, low driving power and wide safe working area. The design of VDMOS is divided into cellular region and terminal area. The design of the terminal structure usually uses the field plate / field limiting ring structure. But using the field board / field limiting ring structure will make the chip large area, high production cost, low performance-price ratio. The terminal structure of .VLD (Variable Lateral Doping) greatly reduces the terminal length, reduces the production cost and improves the performance-price ratio compared with the field board / field limiting ring structure. Is a new, advanced terminal structure. However, due to the late start of VDMOS research and the backward manufacturing process and technology in China, there is basically no product with VLD terminal structure. Therefore, the research of VLD terminal products is of great significance to the development of domestic VLD terminal products and related products. On the basis of a related project, this paper analyzes the working mechanism of VLD and related terminal structure, and designs the corresponding products. The main parameters are as follows: breakdown voltage is more than 606 V, threshold voltage is 2V, on-state voltage drop is less than 1 V, and on-resistance is less than 1.25 V. The main purpose of this paper is to provide a VLD product design for the subsequent related product development. The main contents of this paper are as follows: 1, briefly introduces the terminal theory, based on the process platform of the project partner, designs the process flow. The process steps are optimized by Tsuprem4/Medici software, and the simulation of VDMOS cell part is carried out, which makes the simulation results meet the requirements of the parameter of the project partner. Secondly, the simulation of VDMOS terminal part is carried out by Tsuprem4/Medici software. Firstly, the terminal structure of the field plate / field limiting ring is adopted, and the structure of the field plate / field limiting ring is optimized, and the result that the peak electric field is less than 2x105 V/cm is obtained. On the basis of the field plate / field limiting ring structure, the terminal length is shortened and the VLD structure is designed. The simulation results show that the electric field tends to be uniformly distributed and the terminal length is greatly reduced. Finally, the layout is drawn and the flow sheet test is carried out. At present, some static parameters are obtained as follows: the structure of field limiting ring / field plate terminal basically meets the requirements, while the breakdown voltage of VLD terminal structure is 100V / 400V. The results show that the flow sheet data can not meet the design requirements.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386
【相似文獻(xiàn)】
相關(guān)期刊論文 前10條
1 唐昭煥;胡剛毅;陳光炳;譚開洲;劉勇;羅俊;徐學(xué)良;;A novel structure for improving the SEGR of a VDMOS[J];半導(dǎo)體學(xué)報(bào);2012年04期
2 王英;何杞鑫;方紹華;;高壓功率VDMOS管的設(shè)計(jì)研制[J];電子器件;2006年01期
3 楊東林;孫偉鋒;劉俠;;700V VDMOS設(shè)計(jì)[J];電子器件;2007年02期
4 劉俠;孫偉鋒;王欽;楊東林;;高壓VDMOS電容的研究[J];電子器件;2007年03期
5 蔡小五;海潮和;王立新;陸江;;新型低壓超結(jié)功率VDMOS器件數(shù)值模擬[J];功能材料與器件學(xué)報(bào);2007年05期
6 徐丹;殷景華;王鑫宇;;VDMOS器件微觀結(jié)構(gòu)研究[J];應(yīng)用科技;2007年11期
7 劉剛;蔡小五;韓鄭生;陸江;王立新;夏洋;;國產(chǎn)VDMOS電離輻射環(huán)境中的敏感參數(shù)研究[J];核技術(shù);2008年08期
8 譚開洲;胡剛毅;楊謨?nèi)A;徐世六;張正t，
本文編號(hào)：2234856
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2234856.html
最近更新
教材專著
