8通道Pipeline ADC的研究
發(fā)布時(shí)間：2018-09-05 14:15
【摘要】：隨著無線通信技術(shù)、集成電路的快速發(fā)展,高速高精度的模數(shù)轉(zhuǎn)換器,繼續(xù)成為一個(gè)現(xiàn)代通信系統(tǒng)的主要構(gòu)建模塊。目前,在高速與高精度之間達(dá)到最好折中的模數(shù)轉(zhuǎn)換器只有流水線模數(shù)轉(zhuǎn)換器(Pipeline ADC)。經(jīng)過長期研究,這種結(jié)構(gòu)的單通道Pipeline ADC的性能在特定條件下基本達(dá)到了極限,尤其是轉(zhuǎn)換速率。在這種背景下,多通道Pipeline ADC突破了單通道Pipeline ADC采樣率的瓶頸。但是,通道之間的失配影響著多通道Pipeline ADC的精度。這種失配包括:失調(diào)、增益、帶寬、參考電壓、采樣時(shí)刻等的偏差。目前,隨著電子設(shè)備工作速率的提高,應(yīng)用在其中的ADC的轉(zhuǎn)換速率也需要提高。提高采樣率的方法有兩種,一種是改善工藝,另一種就是用多通道ADC并行工作來達(dá)到較高采樣率,由于目前工藝已經(jīng)比較先進(jìn)了,因此一般采取第二種方法。當(dāng)對(duì)一個(gè)模擬信號(hào)進(jìn)行處理時(shí),可以將信號(hào)通過一個(gè)多路選擇器對(duì)通道進(jìn)行選擇,選中的通道對(duì)此刻的輸入信號(hào)進(jìn)行處理,多通道交替對(duì)模擬輸入信號(hào)進(jìn)行采樣,這樣就可以提高采樣率。因此,本文設(shè)計(jì)了一種8通道的Pipeline ADC,此設(shè)計(jì)中子通道ADC的精度為14比特,采樣率為12.5 MHz,那么8通道就可以獲得100 MHz的采樣率。在0.5μm CSMC CMOS的工藝條件下,根據(jù)增益、帶寬、功耗、噪聲等的折中考慮,確定了子通道ADC由12級(jí)1.5比特和1級(jí)2比特Flash ADC組成。其中,兩相不交疊時(shí)鐘分別控制奇數(shù)子級(jí)與偶數(shù)子級(jí)交替工作,各級(jí)經(jīng)過延遲對(duì)準(zhǔn)與冗余校準(zhǔn),最終由雙端口輸出14位數(shù)字信號(hào)。在8通道的Pipeline ADC的子通道ADC中,設(shè)計(jì)了關(guān)鍵電路模塊:余量增益電路、跨導(dǎo)運(yùn)算放大器、動(dòng)態(tài)比較器、共模反饋電路和延時(shí)校準(zhǔn)電路;在系統(tǒng)級(jí)電路中,設(shè)計(jì)了關(guān)鍵的芯片級(jí)模塊:參考電壓產(chǎn)生電路、帶隙基準(zhǔn)產(chǎn)生電路、偏置電流產(chǎn)生電路、時(shí)鐘控制電路、復(fù)位電路、時(shí)鐘樹。并對(duì)這些模塊以及整個(gè)系統(tǒng)進(jìn)行了仿真,基本能夠達(dá)到本設(shè)計(jì)的要求。最終用0.5μm CSMC CMOS工藝,三層金屬,兩層多晶硅流片,實(shí)現(xiàn)了8通道的Pipeline ADC。用Cadence軟件中的Spectre工具8通道Pipeline ADC系統(tǒng)進(jìn)行仿真,當(dāng)輸入信號(hào)頻率為6.25 MHz時(shí),得到性能參數(shù)有:DNL為+0.65/-0.80 LSB,INL為+0.78/-1.58 LSB,ENOB為12.06bits,SFDR為80.96 dB,SNR為74.3612 dB,達(dá)到了最初設(shè)計(jì)的要求。
[Abstract]:With the rapid development of wireless communication technology and integrated circuits, high speed and high precision analog-to-digital converters continue to be the main building blocks of a modern communication system. At present, only pipelined A / D converter (Pipeline ADC). Is the best compromise between high speed and high precision. After a long period of research, the performance of this kind of single channel Pipeline ADC has basically reached the limit under certain conditions, especially the conversion rate. In this context, multi-channel Pipeline ADC breaks through the bottleneck of single channel Pipeline ADC sampling rate. However, the mismatch between channels affects the accuracy of multichannel Pipeline ADC. This mismatch includes offset, gain, bandwidth, reference voltage, sampling time, and so on. At present, with the improvement of the working rate of electronic equipment, the conversion rate of ADC used in it also needs to be improved. There are two methods to improve the sampling rate, one is to improve the process, the other is to use multi-channel ADC to work in parallel to achieve a higher sampling rate. When an analog signal is processed, the signal can be selected through a multiplexer, the selected channel processes the input signal at the moment, and the analog input signal is sampled alternately. In this way, the sampling rate can be improved. Therefore, an 8-channel Pipeline ADC, is designed. The precision of the neutron channel ADC is 14 bits and the sampling rate is 12.5 MHz,. Then the 8-channel sampling rate of 100 MHz can be obtained. Under the condition of 0.5 渭 m CSMC CMOS, according to the trade-off among gain, bandwidth, power consumption and noise, it is determined that the sub-channel ADC consists of 12 stage 1.5 bits and 1 stage 2 bit Flash ADC. The two-phase non-overlapping clock controls the odd sub-stage and even sub-stage to work alternately. After delayed alignment and redundant calibration, 14 bit digital signals are output from two ports. In the sub-channel ADC of 8-channel Pipeline ADC, the key circuit modules are designed: residual gain circuit, transconductance operational amplifier, dynamic comparator, common-mode feedback circuit and delay calibration circuit. Key chip-level modules are designed: reference voltage generation circuit, bandgap reference generation circuit, bias current generation circuit, clock control circuit, reset circuit, clock tree. These modules and the whole system are simulated and can basically meet the requirements of this design. Finally, with 0.5 渭 m CSMC CMOS process, three layers of metal and two layers of polysilicon wafers, 8-channel Pipeline ADC. is realized. The 8-channel Pipeline ADC system with Spectre tool in Cadence software is simulated. When the input signal frequency is 6.25 MHz, the performance parameters are obtained: 0.65% -0.80 LSB,INL, 0.78% -1.58 LSB,ENOB, 12.06 bits SFDR, 80.96 dB,SNR and 74.3612 dB,.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792
本文編號(hào)：2224533
[Abstract]:With the rapid development of wireless communication technology and integrated circuits, high speed and high precision analog-to-digital converters continue to be the main building blocks of a modern communication system. At present, only pipelined A / D converter (Pipeline ADC). Is the best compromise between high speed and high precision. After a long period of research, the performance of this kind of single channel Pipeline ADC has basically reached the limit under certain conditions, especially the conversion rate. In this context, multi-channel Pipeline ADC breaks through the bottleneck of single channel Pipeline ADC sampling rate. However, the mismatch between channels affects the accuracy of multichannel Pipeline ADC. This mismatch includes offset, gain, bandwidth, reference voltage, sampling time, and so on. At present, with the improvement of the working rate of electronic equipment, the conversion rate of ADC used in it also needs to be improved. There are two methods to improve the sampling rate, one is to improve the process, the other is to use multi-channel ADC to work in parallel to achieve a higher sampling rate. When an analog signal is processed, the signal can be selected through a multiplexer, the selected channel processes the input signal at the moment, and the analog input signal is sampled alternately. In this way, the sampling rate can be improved. Therefore, an 8-channel Pipeline ADC, is designed. The precision of the neutron channel ADC is 14 bits and the sampling rate is 12.5 MHz,. Then the 8-channel sampling rate of 100 MHz can be obtained. Under the condition of 0.5 渭 m CSMC CMOS, according to the trade-off among gain, bandwidth, power consumption and noise, it is determined that the sub-channel ADC consists of 12 stage 1.5 bits and 1 stage 2 bit Flash ADC. The two-phase non-overlapping clock controls the odd sub-stage and even sub-stage to work alternately. After delayed alignment and redundant calibration, 14 bit digital signals are output from two ports. In the sub-channel ADC of 8-channel Pipeline ADC, the key circuit modules are designed: residual gain circuit, transconductance operational amplifier, dynamic comparator, common-mode feedback circuit and delay calibration circuit. Key chip-level modules are designed: reference voltage generation circuit, bandgap reference generation circuit, bias current generation circuit, clock control circuit, reset circuit, clock tree. These modules and the whole system are simulated and can basically meet the requirements of this design. Finally, with 0.5 渭 m CSMC CMOS process, three layers of metal and two layers of polysilicon wafers, 8-channel Pipeline ADC. is realized. The 8-channel Pipeline ADC system with Spectre tool in Cadence software is simulated. When the input signal frequency is 6.25 MHz, the performance parameters are obtained: 0.65% -0.80 LSB,INL, 0.78% -1.58 LSB,ENOB, 12.06 bits SFDR, 80.96 dB,SNR and 74.3612 dB,.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792
【參考文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前1條
1 陳雨;用于高速高精度A/D轉(zhuǎn)化器的MDAC系統(tǒng)分析和設(shè)計(jì)[D];西安電子科技大學(xué);2014年
，本文編號(hào)：2224533
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