【摘要】：數(shù)字化是當(dāng)今頻繁提及的話題,工藝的進(jìn)步促使數(shù)字系統(tǒng)的集成度越來越高,數(shù)據(jù)處理速度越來越快。巨大的性能優(yōu)勢使得許多模擬信號(hào)處理工作被數(shù)字技術(shù)所取代。然而自然界產(chǎn)生的信號(hào),如聲音、光、溫度、壓力等,皆是模擬的方式變化的。作為模擬域與數(shù)字域的接口,模數(shù)轉(zhuǎn)換器的地位仍舊不可取代,但系統(tǒng)對(duì)模數(shù)轉(zhuǎn)換器的速度要求大幅提高,同時(shí)便攜式設(shè)備與智能設(shè)備的普及使得業(yè)界越發(fā)強(qiáng)調(diào)系統(tǒng)的低功耗設(shè)計(jì)。在此背景下,國內(nèi)外高校和公司提出了許多高速低功耗模數(shù)轉(zhuǎn)換器結(jié)構(gòu)。其中基于過零檢測技術(shù)的流水線模數(shù)轉(zhuǎn)換器不僅在系統(tǒng)架構(gòu)上保留了流水線模數(shù)轉(zhuǎn)換器高速高精度的優(yōu)點(diǎn),而且在單級(jí)電路中采用低功耗的過零檢測器和受控電流源替換高功耗的運(yùn)算放大器,大大降低了系統(tǒng)功耗。并且由于不存在反饋環(huán)路,解決了系統(tǒng)穩(wěn)定性的問題,簡化了設(shè)計(jì),也減輕了工藝變化對(duì)系統(tǒng)的影響。本文在55nm CMOS工藝下,完成了一款電源電壓2.5 V,分辨率10位,采樣速率50 MSPS的基于過零檢測技術(shù)的流水線模數(shù)轉(zhuǎn)換器的設(shè)計(jì)。整個(gè)系統(tǒng)共包含10級(jí),其中1級(jí)采樣保持模塊,8級(jí)1.5位的子模數(shù)轉(zhuǎn)換器和1級(jí)2位的并行模數(shù)轉(zhuǎn)換器。為了提高動(dòng)態(tài)范圍和線性度,系統(tǒng)采用全差分結(jié)構(gòu)。過零檢測功能主要依靠一個(gè)五管運(yùn)算放大器完成,并在過零檢測器中加入延遲調(diào)節(jié)單元用以修正工藝、溫度等因素造成的延遲變化。采用改進(jìn)的共源共柵電流鏡,降低了電流鏡關(guān)斷時(shí)對(duì)輸出端的電荷注入。使用改進(jìn)的過零檢測器作為并行模數(shù)轉(zhuǎn)換器的比較單元,在采樣相即可完成對(duì)輸入信號(hào)的量化與編碼,增大了MDAC在保持相中可用的殘差放大時(shí)間。采用失調(diào)誤差前臺(tái)校正與失調(diào)誤差后臺(tái)校正相結(jié)合的方式來修正系統(tǒng)中非理想因素引入失調(diào)誤差,可有效削減模數(shù)轉(zhuǎn)換器輸出動(dòng)態(tài)性能中的靜態(tài)能量。在采樣頻率為50 MSPS,輸入信號(hào)為頻率16.89 MHz弦波信號(hào)的仿真條件下,模數(shù)轉(zhuǎn)換系統(tǒng)的性能為信號(hào)噪聲失真比約為59 dB,無雜散動(dòng)態(tài)范圍約為67 dB,有效位數(shù)約為9.5位,模數(shù)轉(zhuǎn)換器的核心功耗約為27.5 mW。
[Abstract]:Digitization is a topic frequently mentioned nowadays. The progress of technology makes the integration of digital system more and more high and the speed of data processing faster and faster. Great performance advantage makes many analog signal processing work replaced by digital technology. However, the signals produced by nature, such as sound, light, temperature, pressure and so on, are changed in a simulated way. As the interface between analog domain and digital domain, A / D converter is still irreplaceable, but the speed of ADC is greatly improved. At the same time, the popularity of portable devices and smart devices makes the industry pay more attention to the low power design of the system. In this context, universities and companies at home and abroad have proposed many high-speed low-power A-D converter structures. The pipelined A / D converter based on zero crossing detection technology not only retains the advantages of high speed and high precision in the system architecture, but also has the advantages of high speed and high precision. Moreover, the low power zero crossing detector and controlled current source are used to replace the high power operational amplifier in the single stage circuit, which greatly reduces the power consumption of the system. Because there is no feedback loop, the problem of system stability is solved, the design is simplified, and the influence of process change on the system is alleviated. In this paper, a pipelined analog-to-digital converter based on zero-crossing detection technology is designed based on 55nm CMOS technology, which has a power supply voltage of 2.5 V, a resolution of 10 bits and a sampling rate of 50 MSPS. The whole system consists of 10 stages, of which one stage sampling and holding module is 8 stage 1.5 bit sub A / D converter and 1 stage 2 bit parallel A / D converter. In order to improve the dynamic range and linearity, the system adopts a fully differential structure. The function of zero-crossing detection mainly depends on a five-transistor operational amplifier, and the delay adjustment unit is added to the zero-crossing detector to correct the delay caused by the process and temperature. An improved common gate current mirror is used to reduce the charge injection at the output end when the current mirror is turned off. Using the improved zero-crossing detector as the comparator of the parallel analog-to-digital converter, the quantization and coding of the input signal can be completed in the sampling phase, and the residual amplification time of the MDAC in the holding phase is increased. Using the combination of misalignment error foreground correction and offset error background correction to correct the system non-ideal factor and introducing the offset error can effectively reduce the static energy in the output dynamic performance of the analog-to-digital converter. Under the simulation condition that the sampling frequency is 50m SPS and the input signal is 16.89 MHz chord wave signal, the performance of A / D conversion system is about 59 dB, the non-spurious dynamic range is about 67 dB, and the effective bit number is about 9.5 bits. The core power consumption of ADC is about 27.5 MW.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN792

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