【摘要】：隨著集成電路設(shè)計(jì)規(guī)模增大、復(fù)雜度提高、設(shè)計(jì)周期縮短,芯片測(cè)試面臨諸多問(wèn)題需要解決,已成為集成電路發(fā)展的瓶頸,因此可測(cè)性設(shè)計(jì)(Design For testability,DFT)在芯片設(shè)計(jì)中的作用越來(lái)越重要。要實(shí)現(xiàn)完善的測(cè)試,需要考慮多方面測(cè)試要求,如面積開(kāi)銷(xiāo)、測(cè)試功耗、額外引腳需求等,而選擇適用的測(cè)試策略就更為重要,合理應(yīng)用DFT設(shè)計(jì)中的各種策略,從測(cè)試角度而言,可提高芯片的可測(cè)性、提高故障覆蓋率、降低硬件開(kāi)銷(xiāo)及測(cè)試功耗等;從功能設(shè)計(jì)角度而言,合適的測(cè)試策略可使測(cè)試對(duì)功能的影響降到最低。本文針對(duì)YHFT-XX芯片可測(cè)試設(shè)計(jì)的需求,在降低測(cè)試功耗同時(shí)對(duì)可測(cè)性設(shè)計(jì)方法進(jìn)行分析和結(jié)構(gòu)優(yōu)化,基于低功耗分塊測(cè)試技術(shù),在芯片頂層設(shè)計(jì)調(diào)度控制器管理測(cè)試時(shí)鐘及MBIST測(cè)試啟動(dòng)信號(hào),進(jìn)一步降低測(cè)試功耗,在滿(mǎn)足測(cè)試質(zhì)量要求以及降低測(cè)試成本的同時(shí)保證芯片質(zhì)量和上市時(shí)間。本文主要工作如下:一、分析YHFT-XX芯片在可測(cè)性方面面臨的問(wèn)題,基于低功耗分塊測(cè)試提出解決方案。為了降低掃描測(cè)試中組合邏輯功耗,對(duì)部分掃描邏輯插入增強(qiáng)型阻隔門(mén)。針對(duì)芯片低功耗分塊測(cè)試時(shí),內(nèi)部模塊原始端口不可直接訪(fǎng)問(wèn)問(wèn)題,提出旁路結(jié)構(gòu)和Wrapper測(cè)試環(huán)共享兩種方案,實(shí)現(xiàn)對(duì)被測(cè)模塊端口的測(cè)試訪(fǎng)問(wèn),且在YHFT-XX芯片中獲得良好效果,與傳統(tǒng)Wrapper結(jié)構(gòu)相比,Wrapper共享結(jié)構(gòu)面積可減少61.79%,旁路結(jié)構(gòu)可減少87.60%。二、優(yōu)化存儲(chǔ)體內(nèi)建自測(cè)試(Memory Build-In Self Test,MBIST)設(shè)計(jì)中的存儲(chǔ)體旁路結(jié)構(gòu)節(jié)省面積開(kāi)銷(xiāo),減少時(shí)序單元邏輯數(shù)量,掃描測(cè)試功耗也略有降低,尤其設(shè)計(jì)中包含大量存儲(chǔ)體時(shí),可以有效降低硬件開(kāi)銷(xiāo),本文中的方法可根據(jù)具體電路結(jié)構(gòu)和測(cè)試覆蓋率要求執(zhí)行優(yōu)化方案,本文實(shí)驗(yàn)中FFT_Ram_inst存儲(chǔ)體,在三級(jí)異或時(shí)面積節(jié)省50.68%,在FFT_top模塊中掃描測(cè)試功耗降低約1.53%。三、在芯片頂層采用測(cè)試調(diào)度控制器,實(shí)現(xiàn)低功耗測(cè)試,并對(duì)可測(cè)性技術(shù)中的掃描測(cè)試和MBIST進(jìn)行統(tǒng)一測(cè)試管理,該控制器能夠靈活控制測(cè)試啟動(dòng)和測(cè)試結(jié)果反饋,在測(cè)試結(jié)果反饋處,設(shè)計(jì)了MBIST控制器輸出觀(guān)測(cè)鏈,在機(jī)臺(tái)測(cè)試時(shí)可實(shí)現(xiàn)對(duì)故障存儲(chǔ)體定位。通過(guò)測(cè)試策略對(duì)控制器的模式鏈配置,不僅可以減少測(cè)試引腳,而且達(dá)到降低測(cè)試功耗目的。論文中提出的優(yōu)化方案和低功耗測(cè)試控制已經(jīng)應(yīng)用到Y(jié)HFT-XX芯片可測(cè)性設(shè)計(jì)中,且表現(xiàn)出良好的效果。論文中的研究成果對(duì)電子設(shè)計(jì)自動(dòng)化工具的開(kāi)發(fā)也具有一定的參考價(jià)值。
[Abstract]:With the enlargement of IC design scale, the increase of complexity, the shortening of design cycle, the chip testing faces many problems to be solved, which has become the bottleneck of IC development. Therefore, testability design (Design For) plays an increasingly important role in chip design. In order to realize perfect test, we need to consider many kinds of test requirements, such as area overhead, test power consumption, extra pin requirement and so on. It is more important to choose suitable test strategy. From the point of view of testing, it can improve the testability of the chip, improve the fault coverage, reduce the hardware overhead and test power consumption, etc. From the point of view of function design, the appropriate test strategy can minimize the impact of testing on the function. According to the requirement of YHFT-XX chip testability design, this paper analyzes and optimizes the testability design method while reducing the test power consumption. A scheduling controller is designed at the top of the chip to manage the test clock and the MBIST test start signal to further reduce the test power consumption and ensure the chip quality and the time to market while satisfying the test quality requirements and reducing the test cost. The main work of this paper is as follows: firstly, the problems in testability of YHFT-XX chip are analyzed, and a solution based on low power block testing is proposed. In order to reduce the power consumption of combinational logic in scanning test, an enhanced barrier gate is inserted into partial scan logic. In order to solve the problem that the original port of the internal module can not be accessed directly when the chip is divided into blocks with low power consumption, a bypass structure and a Wrapper test ring sharing scheme are proposed to realize the test access to the port of the module under test, and good results are obtained in the YHFT-XX chip. Compared with the traditional Wrapper structure, the area of the shared structure can be reduced by 61.79 and the bypass structure by 87.60. Secondly, the memory bypass structure in the design of Memory Build-In Self Test self-test (MBIST) is optimized to save area overhead, reduce the number of sequential unit logic, and reduce the power consumption of scanning test slightly, especially when a large number of storage bodies are included in the design. The method in this paper can carry out the optimization scheme according to the specific circuit structure and test coverage requirements. In the experiment, the FFT_Ram_inst storage can save 50.68 points in the three-level XOR time area, and the power consumption of scanning test in the FFT_top module can be reduced by 1.53. Thirdly, a test scheduling controller is adopted at the top of the chip to realize low power test, and the scanning test and MBIST in testability technology are managed uniformly. The controller can control test startup and feedback test results flexibly. At the feedback point of test results, the output observation chain of MBIST controller is designed, and the fault storage can be located when the machine is tested. The mode chain configuration of the controller by test strategy can not only reduce the test pin, but also reduce the test power consumption. The proposed optimization scheme and low power test control have been applied to the testability design of YHFT-XX chip and show good results. The research results in this paper also have some reference value for the development of electronic design automation tools.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN402

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本文編號(hào)：2197369