10位Unary-R-2R型DAC性能研究與設(shè)計
發(fā)布時間：2018-08-22 07:13
【摘要】：數(shù)模轉(zhuǎn)換器(DAC,Digital-to-Analog Converter)作為一種將數(shù)字信號轉(zhuǎn)換為模擬信號的轉(zhuǎn)換器,是信號處理系統(tǒng)中的關(guān)鍵模塊之一。電流舵型DAC是主流的高速DAC結(jié)構(gòu),它常用于通信和多媒體領(lǐng)域。隨著移動設(shè)備的快速發(fā)展,系統(tǒng)對芯片的低功耗性能要求越來越高。然而,電流舵型DAC中的單位電流源在極小的工作電流下匹配性會變差,導(dǎo)致電流舵型DAC性能的下降。Unary-R-2R型DAC通過電阻梯的分流特性產(chǎn)生低位電流,從而避免了DAC中的電流源工作電流過低,一定程度上保證了單位電流源的匹配程度。本文首先介紹了數(shù)模轉(zhuǎn)換器的發(fā)展現(xiàn)狀,簡要比較了各式DAC的結(jié)構(gòu)特點、工作原理及主要性能參數(shù),介紹了Unary-R-2R型DAC的結(jié)構(gòu)特點。根據(jù)Unary-R-2R型DAC的結(jié)構(gòu)特點確定了DAC的分段方式,根據(jù)Unary-R-2R型DAC的工作原理建立了理想的行為級模型和相應(yīng)的仿真平臺。本文分析了電阻失配、電流源失配、有限輸出阻抗和RC延遲效應(yīng)這四個實際電路中存在的非理想因素,根據(jù)各個非理想因素的特性對理想的行為級模型做出修改。通過仿真平臺,分別對四個非理想因素影響DAC性能的特點做出了研究。研究結(jié)果表明,電流源失配對DAC性能的影響最大,電阻失配僅影響靜態(tài)性能,有限輸出阻抗對動態(tài)性能的影響較大,RC延遲效應(yīng)在寄生電容較大時對DAC動態(tài)性能影響明顯。最后,利用MATLAB模型得到的結(jié)論基于TSMC 0.13μm 1P8M CMOS工藝設(shè)計了一個10位Unary-R-2R型數(shù)模轉(zhuǎn)換器,并進(jìn)行了相應(yīng)的系統(tǒng)性能仿真。文中主要設(shè)計了基準(zhǔn)源、單位電流源及R-2R電阻梯。其中,為了獲得受溫度影響小的基準(zhǔn)電流,基準(zhǔn)源采用帶隙基準(zhǔn)技術(shù)產(chǎn)生基準(zhǔn)電壓,通過壓流轉(zhuǎn)換形成基準(zhǔn)電流;為了減小有限輸出阻抗對電路性能的影響,在單位電流源中使用了共源共柵結(jié)構(gòu);在R-2R電阻梯部分通過使用多個多晶電阻構(gòu)建電阻塊,減小了各個電阻塊之間的失配,降低了R-2R電阻梯的分流偏差對DAC靜態(tài)性能的影響。系統(tǒng)仿真結(jié)果表明,本文設(shè)計的數(shù)模轉(zhuǎn)換器最大DNL和INL小于0.5LSB。當(dāng)輸入信號頻率為20MHz采樣頻率為300MHz時,DAC的信噪比為65.8d B,無雜散動態(tài)范圍為62.36d B,有效位數(shù)為9.7533。
[Abstract]:As a kind of converter to convert digital signal to analog signal, DACY Digital-to-Analog Converter is one of the key modules in signal processing system. Current-rudder DAC is a mainstream high-speed DAC architecture, which is often used in the field of communication and multimedia. With the rapid development of mobile devices, the low power performance of the system is becoming more and more important. However, the matching of unit current sources in the current-rudder type DAC will become worse under the minimal operating current, which leads to the decline of the performance of the current-rudder type DAC. Unary-R-2R type DAC generates low current through the shunt characteristics of the resistor ladder. Thus the current source working current in DAC is not too low and the matching degree of unit current source is ensured to some extent. This paper first introduces the development of digital-to-analog converters, briefly compares the structural characteristics, working principles and main performance parameters of various DAC, and introduces the structural characteristics of Unary-R-2R type DAC. According to the structural characteristics of Unary-R-2R type DAC, the segmented mode of DAC is determined, and the ideal behavior level model and corresponding simulation platform are established according to the working principle of Unary-R-2R type DAC. In this paper, the nonideal factors in four practical circuits, resistance mismatch, current source mismatch, finite output impedance and RC delay effect, are analyzed, and the ideal behavior level model is modified according to the characteristics of each non-ideal factor. Based on the simulation platform, the characteristics of four non-ideal factors affecting DAC performance are studied. The results show that the current source mismatch has the greatest influence on the DAC performance, the resistance mismatch only affects the static performance, and the limited output impedance has a greater effect on the dynamic performance of DAC. The RC delay effect has a significant effect on the dynamic performance of DAC when the parasitic capacitance is large. Finally, a 10-bit Unary-R-2R digital-to-analog converter is designed based on the TSMC 0.13 渭 m 1P8M CMOS process based on the conclusion of the MATLAB model, and the corresponding system performance simulation is carried out. In this paper, reference source, unit current source and R-2R resistance ladder are designed. In order to obtain the reference current which is less affected by temperature, the reference voltage is generated by bandgap reference technique, and the reference current is formed by voltage-current conversion, and in order to reduce the effect of limited output impedance on circuit performance, The common gate structure is used in the unit current source, and the resistance block is constructed by using multiple polycrystalline resistors in the R-2R resistor ladder, which reduces the mismatch between the resistor blocks and the influence of the shunt deviation of the R-2R resistor ladder on the static performance of DAC. The simulation results show that the maximum DNL and INL of the digital-to-analog converter designed in this paper are less than 0.5 LSB. When the input signal frequency is 20MHz sampling frequency, the signal-to-noise ratio is 65.8 dB, the non-spurious dynamic range is 62.36 dB, and the effective bit number is 9.7533.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792
本文編號：2196353
[Abstract]:As a kind of converter to convert digital signal to analog signal, DACY Digital-to-Analog Converter is one of the key modules in signal processing system. Current-rudder DAC is a mainstream high-speed DAC architecture, which is often used in the field of communication and multimedia. With the rapid development of mobile devices, the low power performance of the system is becoming more and more important. However, the matching of unit current sources in the current-rudder type DAC will become worse under the minimal operating current, which leads to the decline of the performance of the current-rudder type DAC. Unary-R-2R type DAC generates low current through the shunt characteristics of the resistor ladder. Thus the current source working current in DAC is not too low and the matching degree of unit current source is ensured to some extent. This paper first introduces the development of digital-to-analog converters, briefly compares the structural characteristics, working principles and main performance parameters of various DAC, and introduces the structural characteristics of Unary-R-2R type DAC. According to the structural characteristics of Unary-R-2R type DAC, the segmented mode of DAC is determined, and the ideal behavior level model and corresponding simulation platform are established according to the working principle of Unary-R-2R type DAC. In this paper, the nonideal factors in four practical circuits, resistance mismatch, current source mismatch, finite output impedance and RC delay effect, are analyzed, and the ideal behavior level model is modified according to the characteristics of each non-ideal factor. Based on the simulation platform, the characteristics of four non-ideal factors affecting DAC performance are studied. The results show that the current source mismatch has the greatest influence on the DAC performance, the resistance mismatch only affects the static performance, and the limited output impedance has a greater effect on the dynamic performance of DAC. The RC delay effect has a significant effect on the dynamic performance of DAC when the parasitic capacitance is large. Finally, a 10-bit Unary-R-2R digital-to-analog converter is designed based on the TSMC 0.13 渭 m 1P8M CMOS process based on the conclusion of the MATLAB model, and the corresponding system performance simulation is carried out. In this paper, reference source, unit current source and R-2R resistance ladder are designed. In order to obtain the reference current which is less affected by temperature, the reference voltage is generated by bandgap reference technique, and the reference current is formed by voltage-current conversion, and in order to reduce the effect of limited output impedance on circuit performance, The common gate structure is used in the unit current source, and the resistance block is constructed by using multiple polycrystalline resistors in the R-2R resistor ladder, which reduces the mismatch between the resistor blocks and the influence of the shunt deviation of the R-2R resistor ladder on the static performance of DAC. The simulation results show that the maximum DNL and INL of the digital-to-analog converter designed in this paper are less than 0.5 LSB. When the input signal frequency is 20MHz sampling frequency, the signal-to-noise ratio is 65.8 dB, the non-spurious dynamic range is 62.36 dB, and the effective bit number is 9.7533.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792
【參考文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前1條
1 吳苗松;14bit、30Msps自校準(zhǔn)分段式電流舵DAC的設(shè)計[D];電子科技大學(xué);2005年
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