一種快速關(guān)斷溝槽型SOI LDMOS器件
發(fā)布時間：2018-08-18 16:11
【摘要】：圍繞降低溝槽型SOI LDMOS功率器件的優(yōu)值,提出了一種新型多柵溝槽SOI LDMOS器件(MG-TMOS)。與常規(guī)溝槽型SOI LDMOS(C-TMOS)器件相比,新型MG-TMOS器件在不犧牲擊穿電壓的同時,降低了器件開關(guān)切換時充放電的柵漏電荷和器件的比導(dǎo)通電阻。這是因?yàn)?1)新型MG-TMOS器件溝槽里的保護(hù)柵將器件的柵漏電容轉(zhuǎn)換為器件的柵源電容和漏源電容,大幅度降低了器件的柵漏電荷;2)保護(hù)柵偏置電壓的存在使得器件導(dǎo)通時會在溝槽底部形成一層低阻積累層,從而降低器件的導(dǎo)通電阻。仿真結(jié)果表明:該新型溝槽型SOI LDMOS器件的優(yōu)值從常規(guī)器件的503.4mΩ·nC下降到406.6mΩ·nC,實(shí)現(xiàn)了器件的快速關(guān)斷。
[Abstract]:A novel multi-gate grooved SOI LDMOS device (MG-TMOS) is proposed to reduce the superior value of grooved SOI LDMOS power device. Compared with conventional SOI LDMOS (C-TMOS devices, the novel MG-TMOS devices can reduce the gate leakage charge and discharge and the specific on-resistance of the devices without sacrificing the breakdown voltage. This is because the protection gate in the grooves of the new MG-TMOS device converts the device's gate leakage capacitance into the device's gate source capacitance and drain source capacitance. The gate leakage charge of the device is greatly reduced. The existence of the guard gate bias voltage causes the device to form a low resistance accumulation layer at the bottom of the groove when the device is on, thus reducing the on-resistance of the device. The simulation results show that the excellent value of the novel grooved SOI LDMOS device is reduced from 503.4 m 惟 NC to 406.6 m 惟 NC, and the fast turn-off of the device is realized.
【作者單位】： 西南交通大學(xué)信息科學(xué)與技術(shù)學(xué)院;
【基金】：國家自然科學(xué)基金資助項目(61404110)
【分類號】：TN386
本文編號：2189992
[Abstract]:A novel multi-gate grooved SOI LDMOS device (MG-TMOS) is proposed to reduce the superior value of grooved SOI LDMOS power device. Compared with conventional SOI LDMOS (C-TMOS devices, the novel MG-TMOS devices can reduce the gate leakage charge and discharge and the specific on-resistance of the devices without sacrificing the breakdown voltage. This is because the protection gate in the grooves of the new MG-TMOS device converts the device's gate leakage capacitance into the device's gate source capacitance and drain source capacitance. The gate leakage charge of the device is greatly reduced. The existence of the guard gate bias voltage causes the device to form a low resistance accumulation layer at the bottom of the groove when the device is on, thus reducing the on-resistance of the device. The simulation results show that the excellent value of the novel grooved SOI LDMOS device is reduced from 503.4 m 惟 NC to 406.6 m 惟 NC, and the fast turn-off of the device is realized.
【作者單位】： 西南交通大學(xué)信息科學(xué)與技術(shù)學(xué)院;
【基金】：國家自然科學(xué)基金資助項目(61404110)
【分類號】：TN386
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