基本單元電路的NBTI機(jī)制下性能退化分析及改進(jìn)方法研究
發(fā)布時(shí)間：2018-08-16 12:26
【摘要】：自摩爾定律誕生以來,半導(dǎo)體技術(shù)已經(jīng)按照該規(guī)律發(fā)展了半個(gè)世紀(jì)。2013年國際半導(dǎo)體技術(shù)發(fā)展路線圖(ITRS, International Technology Roadmap for Semiconductor)預(yù)測(cè),到2017年半導(dǎo)體器件特征尺寸將達(dá)到7nm。隨著器件尺寸的不斷縮小,當(dāng)柵極氧化層的電場(chǎng)強(qiáng)度升高到高于6MV/cm時(shí),P-MOSFET的負(fù)偏壓溫度不穩(wěn)定性(NBTI, Negative Bias Temperature Instability)成為限制納米器件及集成電路壽命的主導(dǎo)因素。本文詳細(xì)介紹了業(yè)界接受最廣的反應(yīng)擴(kuò)散模型(RD model, Reaction Diffusion model),并基于此模型主要做了如下工作：1.對(duì)傳統(tǒng)的基于SPICE的模擬電路仿真設(shè)計(jì)流程進(jìn)行改進(jìn),在模擬電路設(shè)計(jì)后端增加考慮NBTI效應(yīng)的可靠性分析、改進(jìn)及驗(yàn)證等步驟,使該流程適應(yīng)于納米工藝下的模擬電路設(shè)計(jì),并提高電路抗NBTI退化的能力；2.基于RD模型,對(duì)簡(jiǎn)單電流鏡、Cascode電流鏡、寬擺幅電流鏡等基準(zhǔn)電路中NBTI效應(yīng)的退化進(jìn)行了系統(tǒng)的仿真分析,得到Cascode電流鏡在P-MOSFET晶體管發(fā)生同等退化時(shí)電路的退化最嚴(yán)重,寬擺幅電流鏡電路的退化最小,這可以通過適當(dāng)增加晶體管的寬長(zhǎng)比彌補(bǔ)NBTI退化量。但是輸出電流復(fù)制參考電流的能力沒有受到影響；3.對(duì)單級(jí)放大器、差分放大器、運(yùn)算放大器等放大電路中NBTI效應(yīng)的退化進(jìn)行了系統(tǒng)的仿真分析,結(jié)果表明-3dB帶寬的退化量是所有參數(shù)的退化中最嚴(yán)重的。運(yùn)用可靠性設(shè)計(jì)方法,筆者從電路結(jié)構(gòu)對(duì)兩級(jí)運(yùn)放進(jìn)行改進(jìn),用電流鏡代替電路中的關(guān)鍵器件,通過電流鏡中的電阻R引入反饋,抵消了NBTI退化對(duì)電路的影響,使兩級(jí)運(yùn)放的-3dB帶寬的退化量從27%降到了1%左右,共模抑制比、相位裕度等參數(shù)的退化量被降低到了1%以內(nèi),顯著提高了兩級(jí)運(yùn)放抗NBTI退化的能力。
[Abstract]:Since the birth of Moore's Law, semiconductor technology has been developed in accordance with this law for half a century. The 2013 International Semiconductor Technology Development Roadmap (ITRS, International Technology Roadmap for Semiconductor) predicts that the characteristic size of semiconductor devices will reach 7 nm by 2017. With the decrease of device size, the negative bias temperature instability (NBTI, Negative Bias Temperature Instability) of P-MOSFET becomes the dominant factor limiting the lifetime of nanoscale devices and integrated circuits when the electric field intensity of the gate oxide layer is higher than that of 6MV/cm. In this paper, the most widely accepted reaction-diffusion model, (RD model, Reaction Diffusion model), is introduced in detail and based on this model, the following work is done: 1. The traditional simulation design flow of analog circuit based on SPICE is improved, and the steps of reliability analysis, improvement and verification considering NBTI effect are added to the back end of analog circuit design, so that the flow can be adapted to the analog circuit design under nanotechnology. It also improves the ability of the circuit to resist NBTI degradation. Based on Rd model, the degradation of NBTI effect in reference circuits such as simple current mirror and wide swing current mirror is simulated and analyzed systematically. It is concluded that the degradation of Cascode current mirror is the most serious when the same degradation occurs in P-MOSFET transistors. The degradation of the wide swing current mirror circuit is the least, which can compensate the NBTI degradation by increasing the aspect ratio of the transistor appropriately. But the output current's ability to replicate the reference current is not affected. The degradation of NBTI effect in single-stage amplifiers, differential amplifiers and operational amplifiers is analyzed systematically. The results show that the degradation of -3dB bandwidth is the most serious of all parameters. Using the reliability design method, the author improves the two-stage operational amplifier from the circuit structure, uses the current mirror to replace the key device in the circuit, and introduces feedback through the resistance R in the current mirror, which counteracts the influence of NBTI degradation on the circuit. The degradation of -3dB bandwidth of the two-stage operational amplifier is reduced from 27% to about 1%, and the degradation of the common mode rejection ratio and phase margin is reduced to less than 1%, which greatly improves the ability of the two-stage operational amplifier to resist NBTI degradation.
【學(xué)位授予單位】：華東師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN402
本文編號(hào)：2185978
[Abstract]:Since the birth of Moore's Law, semiconductor technology has been developed in accordance with this law for half a century. The 2013 International Semiconductor Technology Development Roadmap (ITRS, International Technology Roadmap for Semiconductor) predicts that the characteristic size of semiconductor devices will reach 7 nm by 2017. With the decrease of device size, the negative bias temperature instability (NBTI, Negative Bias Temperature Instability) of P-MOSFET becomes the dominant factor limiting the lifetime of nanoscale devices and integrated circuits when the electric field intensity of the gate oxide layer is higher than that of 6MV/cm. In this paper, the most widely accepted reaction-diffusion model, (RD model, Reaction Diffusion model), is introduced in detail and based on this model, the following work is done: 1. The traditional simulation design flow of analog circuit based on SPICE is improved, and the steps of reliability analysis, improvement and verification considering NBTI effect are added to the back end of analog circuit design, so that the flow can be adapted to the analog circuit design under nanotechnology. It also improves the ability of the circuit to resist NBTI degradation. Based on Rd model, the degradation of NBTI effect in reference circuits such as simple current mirror and wide swing current mirror is simulated and analyzed systematically. It is concluded that the degradation of Cascode current mirror is the most serious when the same degradation occurs in P-MOSFET transistors. The degradation of the wide swing current mirror circuit is the least, which can compensate the NBTI degradation by increasing the aspect ratio of the transistor appropriately. But the output current's ability to replicate the reference current is not affected. The degradation of NBTI effect in single-stage amplifiers, differential amplifiers and operational amplifiers is analyzed systematically. The results show that the degradation of -3dB bandwidth is the most serious of all parameters. Using the reliability design method, the author improves the two-stage operational amplifier from the circuit structure, uses the current mirror to replace the key device in the circuit, and introduces feedback through the resistance R in the current mirror, which counteracts the influence of NBTI degradation on the circuit. The degradation of -3dB bandwidth of the two-stage operational amplifier is reduced from 27% to about 1%, and the degradation of the common mode rejection ratio and phase margin is reduced to less than 1%, which greatly improves the ability of the two-stage operational amplifier to resist NBTI degradation.
【學(xué)位授予單位】：華東師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN402
【相似文獻(xiàn)】
相關(guān)期刊論文 前2條
1 朱天文;王宏力;陳堅(jiān);張立波;;基于退化軌跡未知的多退化量可靠度預(yù)測(cè)方法[J];傳感器與微系統(tǒng);2013年02期
2 ;[J];;年期
相關(guān)碩士學(xué)位論文 前2條
1 花修春;基本單元電路的NBTI機(jī)制下性能退化分析及改進(jìn)方法研究[D];華東師范大學(xué);2016年
2 申曄;多退化系統(tǒng)加速退化試驗(yàn)方法與應(yīng)用研究[D];國防科學(xué)技術(shù)大學(xué);2011年
，本文編號(hào)：2185978
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2185978.html
最近更新
教材專著
