快速鎖定的高速低抖動(dòng)時(shí)鐘發(fā)生器的研究與設(shè)計(jì)
發(fā)布時(shí)間：2018-08-09 14:31
【摘要】：隨著經(jīng)濟(jì)社會(huì)的日新月異,移動(dòng)互聯(lián)網(wǎng)的逐漸普及,消費(fèi)類電子產(chǎn)品越來越受到大眾的喜愛。作為消費(fèi)類電子產(chǎn)品中必不可少的時(shí)鐘產(chǎn)生電路,伴隨著數(shù)字信號(hào)處理技術(shù)的高速發(fā)展,通信設(shè)備、電子產(chǎn)品的工作頻率的不斷提高,對(duì)時(shí)鐘發(fā)生器速度與精度的要求也越來越高,因此對(duì)高速低抖動(dòng)時(shí)鐘發(fā)生器的研究具有重要意義。首先,本文闡述了電荷泵鎖相環(huán)的基本原理,以及鎖相環(huán)在鎖定之前的響應(yīng)行為和鎖定狀態(tài)下的線性模型。深入分析了電荷泵鎖相環(huán)的相位噪聲和非理想效應(yīng),并推導(dǎo)了模數(shù)轉(zhuǎn)換器對(duì)系統(tǒng)時(shí)鐘抖動(dòng)的要求,據(jù)此提出了本設(shè)計(jì)中的時(shí)鐘發(fā)生器的性能指標(biāo)并選取了二類三階電荷泵鎖相環(huán)作為本設(shè)計(jì)中的時(shí)鐘發(fā)生器的主體電路。接著,本文介紹了電荷泵鎖相環(huán)各單元模塊的工作原理和主要電路結(jié)構(gòu)。結(jié)合1.2V電源電壓的55nm標(biāo)準(zhǔn)CMOS工藝,在對(duì)該時(shí)鐘發(fā)生器性能指標(biāo)綜合分析的基礎(chǔ)上完成了各單元模塊的設(shè)計(jì),并提出了利用MOSFET反向?qū)ǖ脑?在沒有增加電路復(fù)雜度的前提下實(shí)現(xiàn)了時(shí)鐘發(fā)生器的快速鎖定。最后,利用CADENCE、HSPICE和SPECTRE等模擬集成電路設(shè)計(jì)工具,對(duì)各單元模塊和整個(gè)環(huán)路系統(tǒng)進(jìn)行了仿真驗(yàn)證,并完成了整個(gè)環(huán)路系統(tǒng)的版圖設(shè)計(jì)。仿真結(jié)果表明:在溫度為25℃,TT工藝角下,時(shí)鐘發(fā)生器輸出1.62GHz方波信號(hào)時(shí)的時(shí)鐘抖動(dòng)為2.27ps,鎖定時(shí)間為3.3μs。在1.2V電源電壓下,系統(tǒng)的總功耗為4.28mW。最終版圖面積為1109*1054μm2。
[Abstract]:With the rapid development of economy and society and the popularity of mobile internet, consumer electronic products are more and more popular. As an indispensable clock generation circuit in consumer electronic products, with the rapid development of digital signal processing technology, communication equipment, electronic products working frequency continues to improve, The speed and precision of clock generator are required more and more, so the research of high speed and low jitter clock generator is of great significance. Firstly, the basic principle of charge pump phase-locked loop (CPPLL), the response behavior of PLL before locking and the linear model of PLL under locking state are described. The phase noise and non-ideal effect of the charge pump phase-locked loop (CPPLL) are analyzed in depth, and the requirements of A / D converter for system clock jitter are derived. Based on this, the performance index of the clock generator in this design is put forward, and the second kind of third order charge pump phase-locked loop is selected as the main circuit of the clock generator in this design. Then, this paper introduces the working principle and main circuit structure of each unit module of the charge pump phase-locked loop. Combined with 55nm standard CMOS process with 1.2V power supply voltage, the design of each unit module is completed on the basis of synthetically analyzing the performance index of the clock generator, and the principle of using MOSFET reverse conduction is put forward. The fast locking of the clock generator is realized without increasing the complexity of the circuit. Finally, the simulation of each unit module and the whole loop system is carried out by using the analog integrated circuit design tools such as CADENCEN HSpice and SPECTRE, and the layout design of the whole loop system is completed. The simulation results show that the clock jitter is 2.27 psand the locking time is 3.3 渭 s when the clock generator outputs the 1.62GHz square wave signal at 25 鈩，
本文編號(hào)：2174381
[Abstract]:With the rapid development of economy and society and the popularity of mobile internet, consumer electronic products are more and more popular. As an indispensable clock generation circuit in consumer electronic products, with the rapid development of digital signal processing technology, communication equipment, electronic products working frequency continues to improve, The speed and precision of clock generator are required more and more, so the research of high speed and low jitter clock generator is of great significance. Firstly, the basic principle of charge pump phase-locked loop (CPPLL), the response behavior of PLL before locking and the linear model of PLL under locking state are described. The phase noise and non-ideal effect of the charge pump phase-locked loop (CPPLL) are analyzed in depth, and the requirements of A / D converter for system clock jitter are derived. Based on this, the performance index of the clock generator in this design is put forward, and the second kind of third order charge pump phase-locked loop is selected as the main circuit of the clock generator in this design. Then, this paper introduces the working principle and main circuit structure of each unit module of the charge pump phase-locked loop. Combined with 55nm standard CMOS process with 1.2V power supply voltage, the design of each unit module is completed on the basis of synthetically analyzing the performance index of the clock generator, and the principle of using MOSFET reverse conduction is put forward. The fast locking of the clock generator is realized without increasing the complexity of the circuit. Finally, the simulation of each unit module and the whole loop system is carried out by using the analog integrated circuit design tools such as CADENCEN HSpice and SPECTRE, and the layout design of the whole loop system is completed. The simulation results show that the clock jitter is 2.27 psand the locking time is 3.3 渭 s when the clock generator outputs the 1.62GHz square wave signal at 25 鈩，
本文編號(hào)：2174381
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