發(fā)布時(shí)間：2018-08-07 18:03

【摘要】：隨著云計(jì)算、大數(shù)據(jù)、物聯(lián)網(wǎng)等技術(shù)的快速發(fā)展,人們對(duì)通信系統(tǒng)的帶寬要求日益增加,但同時(shí)又希望將功耗控制在合理的范圍之內(nèi)。因此,如何以低成本可靠地傳輸高速數(shù)據(jù)受到越來(lái)越多的關(guān)注。本文研究了高速鏈路均衡電路的能效優(yōu)化,對(duì)在給定速率、信道、鏈路指標(biāo)等條件下尋找出能效最優(yōu)均衡結(jié)構(gòu)的方法進(jìn)行了研究。利用統(tǒng)計(jì)分析技術(shù),得到符合鏈路約束條件的多種均衡結(jié)構(gòu)組合；利用能效建模技術(shù),可以得到各均衡器在不同速率下的能效,通過(guò)兩種技術(shù)結(jié)合便可從滿(mǎn)足鏈路約束條件的眾多均衡結(jié)構(gòu)組合中篩選出能效優(yōu)化方案,具有實(shí)用性和準(zhǔn)確度。本文還研究了分?jǐn)?shù)間隔前饋均衡器的設(shè)計(jì)與實(shí)現(xiàn),采用0.18μmCMOS工藝設(shè)計(jì)了6.25Gb/s+的4抽頭,抽頭間隔為1/3符號(hào)周期的連續(xù)時(shí)間前饋均衡器。有源延時(shí)線采用源極電容衰減結(jié)構(gòu)拓展帶寬,并采用電容和電阻校準(zhǔn)技術(shù)減輕工藝角變化對(duì)電路性能的影響,輸出緩沖級(jí)借助片上電感提供增益和擴(kuò)展帶寬。該均衡器版圖面積為0.49mmm2(含焊盤(pán)),已經(jīng)流片。后仿真結(jié)果表明,對(duì)于經(jīng)過(guò)24英寸PCB信道的6.25Gb/s偽隨機(jī)序列信號(hào)和經(jīng)過(guò)18英寸PCB信道的10Gb/s偽隨機(jī)序列信號(hào),該均衡器可以在碼間干擾非常嚴(yán)重的情況下,有效改善眼圖。在通信系統(tǒng)飛速發(fā)展的今天,本文研究的均衡電路能效優(yōu)化流程有助于解決高速鏈路面臨的速度和功耗矛盾,所設(shè)計(jì)和實(shí)現(xiàn)的前饋均衡器對(duì)于高速接收機(jī)的實(shí)現(xiàn)具有重要意義。
[Abstract]:With the rapid development of cloud computing, big data, Internet of things and other technologies, the bandwidth requirements of communication systems are increasing day by day, but at the same time, we hope to control the power consumption within a reasonable range. Therefore, how to transmit high-speed data with low cost and reliability has attracted more and more attention. In this paper, the energy efficiency optimization of high speed link equalization circuit is studied, and the method of finding the optimal equalization structure of energy efficiency under the given rate, channel, link index and so on is studied. By using the statistical analysis technique, we can obtain a variety of equalization structures that meet the link constraint conditions, and by using the energy efficiency modeling technology, we can get the energy efficiency of each equalizer at different rates. The energy efficiency optimization scheme can be selected from the combination of many equalization structures which satisfy the link constraint condition by combining the two techniques. It has practicability and accuracy. In this paper, the design and implementation of fractional interval feedforward equalizer are also studied. The 4-tap of 6.25Gb/s is designed by using 0.18 渭 mCMOS process, and the continuous time feedforward equalizer with 1 / 3 symbol period is designed. The active delay line uses the source capacitor attenuation structure to expand the bandwidth, and adopts the capacitance and resistance calibration technology to reduce the influence of the process angle change on the circuit performance. The output buffer stage provides the gain and the expanded bandwidth with the help of on-chip inductance. The equalizer layout area is 0.49mmm2 (including solder pad) and has been flattened. The post-simulation results show that the equalizer can effectively improve the eye diagram of 6.25Gb/s pseudorandom sequence signals over 24-inch PCB channel and 10Gb/s pseudorandom sequence signals over 18-inch PCB channel under very serious inter-symbol interference. With the rapid development of communication system, the energy efficiency optimization flow of equalization circuit studied in this paper is helpful to solve the contradiction between speed and power consumption in high speed link. The feedforward equalizer designed and implemented is of great significance to the realization of high speed receiver.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類(lèi)號(hào)】：TN715

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1 李峰燈;高速鏈路均衡電路的能效優(yōu)化及分?jǐn)?shù)間隔FFE設(shè)計(jì)[D];東南大學(xué);2016年

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本文編號(hào)：2170882