基于FPGA的串行RapidIO接口的設計與實現(xiàn)
發(fā)布時間：2018-08-05 15:18
【摘要】：隨著嵌入式處理器性能的不斷提升,傳統(tǒng)的并行總線互連方案已經(jīng)滿足不了其日益增長的帶寬需求。取而代之的Rapid IO互連技術具有速率高、成本低、引腳數(shù)少等優(yōu)點,可以滿足高性能嵌入式系統(tǒng)的廣泛需求。作為當前嵌入式領域內(nèi)唯一得到授權(quán)的國際標準,Rapid IO也是未來解決高性能嵌入式互連的最佳方案。目前,世界上幾乎所有的嵌入式主流廠商都已經(jīng)支持Rapid IO互連技術,并源源不斷地推出各種基于Rapid IO規(guī)范的產(chǎn)品,涵蓋了各種開發(fā)工具、嵌入式系統(tǒng)、IP、軟件、測試設備以及半導體產(chǎn)品等。本論文對Rapid IO互連協(xié)議進行了研究,并參考相關產(chǎn)品的技術文檔設計實現(xiàn)了一款基于RapidIO協(xié)議的串行互連接口。該接口實現(xiàn)了數(shù)據(jù)包的組包和解包、數(shù)據(jù)包的有序收發(fā)、初始化操作以及接收方控制的流量控制等基本功能。論文中首先介紹了有關Rapid IO互連技術的研究背景和國內(nèi)外發(fā)展現(xiàn)狀,然后分析了Rapid IO互連協(xié)議的分層體系結(jié)構(gòu)、典型操作流程、常用操作類型、各種數(shù)據(jù)單元的格式和流量控制等內(nèi)容,最后根據(jù)需要提取了協(xié)議中串行鏈路部分的基本功能,并提出串行Rapid IO接口電路的總體設計方案�；赥op-Down的設計思路和模塊化的設計方法,使用Verilog硬件描述語言設計實現(xiàn)了組包邏輯、解包邏輯、邏輯層調(diào)度邏輯、初始化狀態(tài)機、發(fā)送通道、接收通道以及重傳恢復狀態(tài)機等主要功能模塊;為了減小設計的難度,高速串行收發(fā)電路采用Xilinx公司的FPGA中的Rocket IO硬核IP實現(xiàn)。此外,本文還分析了電路的時鐘域劃分和時鐘分配,對異步信號的交互進行了跨時鐘域處理。最后基于Modelsim軟件搭建了仿真驗證平臺,對所設計的串行Rapid IO接口電路分別進行了模塊級仿真和整體仿真。FPGA下板測試結(jié)果顯示,本論文中所設計的串行Rapid IO接口電路功能正確。
[Abstract]:With the improvement of embedded processor performance, the traditional parallel bus interconnection scheme can not meet its growing bandwidth requirements. Instead of Rapid IO interconnection technology, it has the advantages of high speed, low cost and fewer pins, so it can meet the needs of high performance embedded systems. As the only authorized international standard in embedded field, Rapid IO is the best way to solve high performance embedded interconnection in the future. At present, almost all the mainstream embedded manufacturers in the world have supported the Rapid IO interconnection technology, and have continuously introduced a variety of products based on the Rapid IO specification, covering all kinds of development tools, embedded systems, IPOs, software, etc. Test equipment and semiconductor products. In this paper, the Rapid IO interconnection protocol is studied, and a serial interconnect interface based on RapidIO protocol is designed and implemented by referring to the technical documents of related products. The interface realizes the basic functions of packet formation and unpacking, packet sending and receiving orderly, initialization operation and flow control controlled by receiver, etc. This paper first introduces the research background of Rapid IO interconnection technology and its development status at home and abroad, then analyzes the layered architecture, typical operation flow, common operation types of Rapid IO interconnection protocol. Finally, the basic functions of serial link part in the protocol are extracted according to the need, and the overall design scheme of serial Rapid IO interface circuit is put forward. Based on the design idea and modular design method of Top-Down, this paper uses Verilog hardware description language to design and implement packet grouping logic, unpacking logic, logic layer scheduling logic, initialization state machine, sending channel, and so on. In order to reduce the difficulty of design, the high-speed serial transceiver is implemented by Rocket IO hard core IP in FPGA of Xilinx Company. In addition, the clock domain division and clock allocation of the circuit are analyzed, and the cross-clock domain processing of asynchronous signal interaction is carried out. Finally, the simulation platform is built based on Modelsim software. The module level simulation and the whole simulation. The test results show that the serial Rapid IO interface circuit designed in this paper has the correct function.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TP334.7;TN791
本文編號：2166191
[Abstract]:With the improvement of embedded processor performance, the traditional parallel bus interconnection scheme can not meet its growing bandwidth requirements. Instead of Rapid IO interconnection technology, it has the advantages of high speed, low cost and fewer pins, so it can meet the needs of high performance embedded systems. As the only authorized international standard in embedded field, Rapid IO is the best way to solve high performance embedded interconnection in the future. At present, almost all the mainstream embedded manufacturers in the world have supported the Rapid IO interconnection technology, and have continuously introduced a variety of products based on the Rapid IO specification, covering all kinds of development tools, embedded systems, IPOs, software, etc. Test equipment and semiconductor products. In this paper, the Rapid IO interconnection protocol is studied, and a serial interconnect interface based on RapidIO protocol is designed and implemented by referring to the technical documents of related products. The interface realizes the basic functions of packet formation and unpacking, packet sending and receiving orderly, initialization operation and flow control controlled by receiver, etc. This paper first introduces the research background of Rapid IO interconnection technology and its development status at home and abroad, then analyzes the layered architecture, typical operation flow, common operation types of Rapid IO interconnection protocol. Finally, the basic functions of serial link part in the protocol are extracted according to the need, and the overall design scheme of serial Rapid IO interface circuit is put forward. Based on the design idea and modular design method of Top-Down, this paper uses Verilog hardware description language to design and implement packet grouping logic, unpacking logic, logic layer scheduling logic, initialization state machine, sending channel, and so on. In order to reduce the difficulty of design, the high-speed serial transceiver is implemented by Rocket IO hard core IP in FPGA of Xilinx Company. In addition, the clock domain division and clock allocation of the circuit are analyzed, and the cross-clock domain processing of asynchronous signal interaction is carried out. Finally, the simulation platform is built based on Modelsim software. The module level simulation and the whole simulation. The test results show that the serial Rapid IO interface circuit designed in this paper has the correct function.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TP334.7;TN791
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，本文編號：2166191
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