【摘要】：依據(jù)ATA6協(xié)議,在FPGA上設(shè)計(jì)對(duì)IDE硬盤(pán)的控制模塊,同時(shí)使用Xilinx的多端口內(nèi)存控制器MPMC IP核,實(shí)現(xiàn)能夠訪(fǎng)問(wèn)外部DDR2_SDRAM的NPI接口控制器。在此基礎(chǔ)上,利用嵌入式FPGA開(kāi)發(fā)環(huán)境,設(shè)計(jì)頂層控制IP核,完成硬盤(pán)控制器與NPI接口的有效銜接。在Micro Blaze的控制下,數(shù)據(jù)在硬盤(pán)與DDR2_SDRAM之間直接高速傳輸,實(shí)現(xiàn)了高性能DMA控制器的功能,從而提高了主機(jī)CPU利用率。設(shè)計(jì)在Xilinx的XUPV5_LX110T開(kāi)發(fā)平臺(tái)得到了驗(yàn)證。
[Abstract]:According to the ATA6 protocol, the control module of the IDE hard disk is designed on the FPGA, and the MPMC IP core of the Xilinx multi-port memory controller is used to realize the NPI interface controller which can access the external DDR2_SDRAM. On this basis, the top control IP core is designed by using the embedded FPGA development environment, and the interface between the hard disk controller and the NPI is effectively connected. Under the control of Micro Blaze, the data is transmitted directly between the hard disk and DDR2_SDRAM at high speed, which realizes the function of high performance DMA controller, and improves the utilization rate of host CPU. The design is verified in the XUPV5_LX110T development platform of Xilinx.
【作者單位】： 山西職業(yè)技術(shù)學(xué)院電子信息工程系;太原理工大學(xué)機(jī)械工程學(xué)院;太原理工大學(xué)礦業(yè)工程學(xué)院;
【基金】：國(guó)家自然科學(xué)基金青年科學(xué)基金項(xiàng)目(61303207) 教育部2012年高等學(xué)校博士學(xué)科點(diǎn)專(zhuān)項(xiàng)科研基金聯(lián)合課題項(xiàng)目(20121402120020) 山西省科學(xué)技術(shù)發(fā)展項(xiàng)目工業(yè)部分(20120321024-01)
【分類(lèi)號(hào)】：TN791;TP332
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本文編號(hào)：2165547