【摘要】：現(xiàn)代電子設(shè)備對(duì)于采樣速率的需求越來(lái)越高,時(shí)間交替并行采樣模數(shù)轉(zhuǎn)換器(Time-Interleaved ADC, TIADC)是一種有效的方法,它能夠保證單通道ADC的采樣精度,同時(shí)大幅提高系統(tǒng)采樣率。但是TIADC系統(tǒng)中存在的增益誤差(Gain error)、偏置誤差(offset error)和時(shí)鐘偏斜誤差(time skew error)嚴(yán)重影響著系統(tǒng)的性能,因此,TIADC系統(tǒng)通道失配誤差的校正成為了研究熱點(diǎn)。文章給出了一種基于完美重構(gòu)的誤差校正算法以及算法的全并行實(shí)現(xiàn)結(jié)構(gòu)。通過(guò)查閱大量的文獻(xiàn)資料,對(duì)TIADC系統(tǒng)的基本原理和誤差進(jìn)行了研究和分析。誤差校正算法的關(guān)鍵在于校正濾波器的設(shè)計(jì),采用加權(quán)最小二乘法對(duì)其進(jìn)行改善,并且在實(shí)現(xiàn)上進(jìn)行改進(jìn),使得該算法在保證性能的基礎(chǔ)上,得以適用于更高的頻率范圍。在校正算法的研究上,本文采用基于正弦擬合的通道失配估算方法對(duì)誤差估計(jì)算法進(jìn)行了研究,給出了基于完美重構(gòu)的校正濾波器的設(shè)計(jì),在最小二乘法的基礎(chǔ)上,采用了加權(quán)最小二乘法對(duì)校正濾波器進(jìn)行改進(jìn),使得系統(tǒng)性能得到大幅改善。在校正電路的研究上,采用全并行結(jié)構(gòu),利用串并轉(zhuǎn)換實(shí)現(xiàn)高速數(shù)據(jù)的降速,再利用濾波器的多相分解技術(shù)構(gòu)建濾波器陣列對(duì)時(shí)鐘失配誤差進(jìn)行實(shí)時(shí)校正,提高了電路的吞吐量。最后,基于FPGA實(shí)現(xiàn)了四通道12bit 800MSPS的TIADC系統(tǒng)。所設(shè)計(jì)的校正電路實(shí)現(xiàn)簡(jiǎn)單,性能良好。Modelsim和MATLAB平臺(tái)上的仿真與分析結(jié)果均表明,校正后TIADC系統(tǒng)的性能和校正前相比得到了大幅提高,并滿足設(shè)計(jì)要求。
[Abstract]:The demand of sampling rate for modern electronic equipment is increasing. Time-Interleaved ADC, TIADC) is an effective method, which can guarantee the sampling accuracy of single channel ADC and greatly improve the sampling rate of the system. However, the gain error, (Gain error), bias error (offset error) and clock skew error (time skew error) exist in TIADC system seriously affect the performance of the system, so the correction of channel mismatch error in TIADC system has become a hot research topic. In this paper, an error correction algorithm based on perfect reconstruction and its full parallel implementation structure are presented. The basic principle and error of TIADC system are studied and analyzed by consulting a lot of documents. The key of the error correction algorithm is the design of the correction filter, which is improved by the weighted least square method and improved in the implementation, so that the algorithm can be applied to a higher frequency range on the basis of ensuring the performance. In this paper, the error estimation algorithm based on sinusoidal fitting is studied, and the design of correction filter based on perfect reconstruction is given. The weighted least square method is used to improve the correction filter, and the system performance is greatly improved. In the research of correction circuit, the parallel structure is adopted to realize the speed reduction of high speed data by using series-parallel conversion, and the filter array is constructed to correct the clock mismatch error in real time by using the polyphase decomposition technology of the filter. The throughput of the circuit is improved. Finally, a four-channel 12bit 800MSPS TIADC system is implemented based on FPGA. The results of simulation and analysis on the platform of .Modelsim and MATLAB show that the performance of the corrected TIADC system has been greatly improved compared with that of the pre-calibration system, and meets the design requirements.
【學(xué)位授予單位】：北京化工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN713

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 徐以濤,沈良,王金龍;FPGA技術(shù)在軟件無(wú)線電中的應(yīng)用[J];電信科學(xué);2001年11期

2 樊民革;趙剡;;一種消除異步電路亞穩(wěn)態(tài)的邏輯控制方法[J];電子測(cè)量技術(shù);2008年10期

相關(guān)碩士學(xué)位論文 前1條

1 范建俊;分時(shí)交替ADC時(shí)鐘失配數(shù)字校準(zhǔn)設(shè)計(jì)與FPGA實(shí)現(xiàn)[D];電子科技大學(xué);2011年

，

本文編號(hào)：2164205