基于FPGA的混合自旋鉆石鏈Ising模型的蒙特卡洛模擬
發(fā)布時(shí)間：2018-07-28 14:08
【摘要】：Ising模型憑借它簡(jiǎn)單的結(jié)構(gòu)和豐富的內(nèi)涵等優(yōu)點(diǎn)在物理統(tǒng)計(jì)中得到廣泛的應(yīng)用,研究混合自旋鉆石鏈Ising模型的磁性質(zhì)對(duì)于一些具有自旋阻挫效應(yīng)的化合物材料的實(shí)驗(yàn)和應(yīng)用研究有一定的指導(dǎo)意義,Ising模型的數(shù)值模擬需要大量的計(jì)算工作,微型計(jì)算機(jī)由于受到總線位寬的限制,其計(jì)算所需時(shí)間會(huì)相對(duì)較長(zhǎng);FPGA憑借其在并行計(jì)算方面的顯著優(yōu)勢(shì)可以大大縮短模擬Ising模型所需要的時(shí)間。首先,本文對(duì)一維鉆石鏈狀I(lǐng)sing模型進(jìn)行了理論介紹,并通過探討蒙特卡洛方法對(duì)該模型的模擬,設(shè)計(jì)總結(jié)出模型的硬件實(shí)現(xiàn)方法,使得模型狀態(tài)能夠進(jìn)行并行更新。其次,本文以FPGA為平臺(tái),使用Verilog硬件描述語言設(shè)計(jì)并實(shí)現(xiàn)了根據(jù)能量變換來更新自旋狀態(tài)的一維鉆石鏈Ising模型,在設(shè)計(jì)過程中,由于模型中格點(diǎn)數(shù)量龐大,占用資源過多,為節(jié)省資源本文采用串并聯(lián)結(jié)合的設(shè)計(jì)方法,既使得模型更新速度得到提升,又節(jié)省了邏輯資源。然后,為方便對(duì)Ising模型的數(shù)據(jù)進(jìn)行分析研究,本文設(shè)計(jì)了一個(gè)圍繞模型的一個(gè)系統(tǒng)。系統(tǒng)包括數(shù)據(jù)產(chǎn)生模塊,存儲(chǔ)模塊,數(shù)據(jù)處理模塊和控制模塊。系統(tǒng)的核心部分是數(shù)據(jù)產(chǎn)生模塊,也就是Ising模型的功能仿真模塊,在每個(gè)時(shí)鐘沿存儲(chǔ)器模塊都會(huì)存儲(chǔ)所有自旋的當(dāng)前狀態(tài),數(shù)據(jù)處理模塊從存儲(chǔ)模塊讀入并處理數(shù)據(jù);最后通過傳輸模塊將數(shù)據(jù)通過URAT傳輸?shù)接?jì)算機(jī)并顯示出來。上述的整個(gè)過程都是由控制模塊控制各個(gè)模塊的使能端將數(shù)據(jù)進(jìn)行有序的傳輸?shù)摹Ｗ詈?本文對(duì)一維鉆石鏈狀I(lǐng)sing模型在FPGA上的功能實(shí)現(xiàn)和數(shù)據(jù)的傳輸?shù)目傮w方案以及各個(gè)模塊的軟硬件實(shí)現(xiàn)進(jìn)行了詳盡的描述,并通過與在微型計(jì)算機(jī)上的模擬進(jìn)行比較,證明Ising模型在FPGA上的狀態(tài)更新速度是在普通計(jì)算機(jī)上的上百倍。
[Abstract]:Ising model is widely used in physical statistics by virtue of its simple structure and rich connotation. The study of the magnetic properties of the mixed spin diamond chain Ising model has a certain guiding significance for the experimental and applied study of some compound materials with spin buckling effect. The numerical simulation of the Ising model requires a lot of computational work. Due to the limitation of bus bit width, the computing time of microcomputer is relatively long. With its remarkable advantage in parallel computing, the time required to simulate Ising model can be greatly shortened. Firstly, the one-dimensional diamond chain Ising model is introduced theoretically, and the simulation of the model by Monte Carlo method is discussed. The hardware implementation method of the model is designed and summarized, which enables the model state to be updated in parallel. Secondly, based on FPGA and Verilog hardware description language, the one-dimensional diamond chain Ising model is designed and implemented to update the spin state according to the energy transformation. In the design process, because of the large number of lattice points in the model, it takes up too much resources. In order to save resources, this paper adopts the design method of series-parallel connection, which not only improves the updating speed of the model, but also saves the logical resources. Then, in order to analyze and study the data of Ising model, a system around the model is designed in this paper. The system includes a data generation module, a storage module, a data processing module and a control module. The core of the system is the data generation module, which is the function simulation module of the Ising model. The current state of all spin is stored in each clock along the memory module, and the data processing module reads in and processes the data from the storage module. Finally, the data is transmitted to the computer through URAT and displayed through the transmission module. The whole process is controlled by the control module. Finally, this paper describes in detail the function realization of one-dimensional diamond chain Ising model on FPGA, the overall scheme of data transmission and the hardware and software implementation of each module, and compares it with the simulation on microcomputer. It is proved that the state update speed of Ising model on FPGA is hundreds of times faster than that on ordinary computer.
【學(xué)位授予單位】：燕山大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791
本文編號(hào)：2150460
[Abstract]:Ising model is widely used in physical statistics by virtue of its simple structure and rich connotation. The study of the magnetic properties of the mixed spin diamond chain Ising model has a certain guiding significance for the experimental and applied study of some compound materials with spin buckling effect. The numerical simulation of the Ising model requires a lot of computational work. Due to the limitation of bus bit width, the computing time of microcomputer is relatively long. With its remarkable advantage in parallel computing, the time required to simulate Ising model can be greatly shortened. Firstly, the one-dimensional diamond chain Ising model is introduced theoretically, and the simulation of the model by Monte Carlo method is discussed. The hardware implementation method of the model is designed and summarized, which enables the model state to be updated in parallel. Secondly, based on FPGA and Verilog hardware description language, the one-dimensional diamond chain Ising model is designed and implemented to update the spin state according to the energy transformation. In the design process, because of the large number of lattice points in the model, it takes up too much resources. In order to save resources, this paper adopts the design method of series-parallel connection, which not only improves the updating speed of the model, but also saves the logical resources. Then, in order to analyze and study the data of Ising model, a system around the model is designed in this paper. The system includes a data generation module, a storage module, a data processing module and a control module. The core of the system is the data generation module, which is the function simulation module of the Ising model. The current state of all spin is stored in each clock along the memory module, and the data processing module reads in and processes the data from the storage module. Finally, the data is transmitted to the computer through URAT and displayed through the transmission module. The whole process is controlled by the control module. Finally, this paper describes in detail the function realization of one-dimensional diamond chain Ising model on FPGA, the overall scheme of data transmission and the hardware and software implementation of each module, and compares it with the simulation on microcomputer. It is proved that the state update speed of Ising model on FPGA is hundreds of times faster than that on ordinary computer.
【學(xué)位授予單位】：燕山大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791
【參考文獻(xiàn)】
相關(guān)期刊論文 前3條
1 李立奇;王宗笠;;二維微正則Ising模型臨界相變的Q2R方法[J];重慶大學(xué)學(xué)報(bào)(自然科學(xué)版);2006年11期
2 韓旭;鄭磊;;基于FPGA的任意波形發(fā)生器的設(shè)計(jì)與實(shí)現(xiàn)[J];電子測(cè)量技術(shù);2013年07期
3 周慶;黃黨志;;基于Ising模型的QR碼加密算法[J];計(jì)算機(jī)應(yīng)用;2013年10期
，本文編號(hào)：2150460
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