【摘要】：功率芯片組封裝必須妥善解決散熱問題,堆疊封裝尤其需要重視,因為堆疊使散熱面積縮小,熱積聚現象將更加明顯,有關這一類問題的研究報道很多,但是功率器件堆疊封裝的產品并不多見,因此,如何在現有技術體系中通過結構設計、流程重整和關鍵工藝改良解決上述問題,是這一類新產品開發(fā)過程中必須面對的課題。本項目研究圍繞一種新型功率器件模組產品QFN3.5x5的堆疊封裝技術開發(fā)展開,該模組包含兩個MOSFET功率器件芯片和一個控制電路IC芯片,研究的目標是形成散熱結構合理的堆疊封裝架構,以便在體積顯著縮小的同時,維持良好熱穩(wěn)定性,重點是開發(fā)堆疊封裝成套工藝,完成模組封裝和關鍵特性測試。為此,首先通過論證確立了堆疊封裝的整體結構設計,然后通過Abaqus軟件進行仿真分析,優(yōu)化封裝結構;接著,針對該優(yōu)化的封裝結構,提出封裝工藝流程設計方案,據此整合已有單元工藝,優(yōu)化關鍵單項技術,形成模塊封裝成套工藝,完成模組批量試生產及熱應力特性測試。所提出的整體封裝架構是在主體的銅引線框架雙側表面分別貼裝一塊MOSFET功率芯片,然后在上管芯之上堆疊控制電路IC芯片,再通過引線鍵合互連并塑封。采用導熱能力突出的銅片作為主體結構就是為了更好地解決功率芯片的熱量導出問題。封裝工藝全流程可以分為兩個部分,即晶圓級預處理工藝模塊和組裝鍵合工藝模塊。晶圓級預處理工藝包括以下主要工序:晶圓正面化學鍍NiAu--植高鉛錫球--回流焊--清洗--晶圓正面用環(huán)氧樹脂塑封--正面減薄露出鉛錫電極--晶圓背面減薄--蒸鍍Ti Ni Ag金屬層。組裝鍵合工藝模塊流程如下:用高鉛焊錫料倒裝粘結下管芯片--用高鉛焊錫料粘結上管芯片和銅片--清洗--堆疊IC芯片到銅片上--固化絕緣膠--引線鍵合--塑封--后道切割等。圍繞如何打通上述封裝工藝全流程,實現良好封裝效果,在現有的DrMOS封裝工藝線基礎上,重點研究了高鉛錫球植球工藝、晶圓正面環(huán)氧樹脂塑封工藝、下管芯片高鉛焊錫料倒裝粘結工藝、上管芯片高鉛焊錫料粘結銅片工藝、以及清洗工藝等單項技術。其中,氋鉛錫球植球借用成熟的絲網印刷技術,根據本產品的特點開發(fā)了專用的絲網以符合產品的要求。圓晶減薄有助于快速散熱,但是減薄操作容易發(fā)生碎裂或其他破損,影響成品率,晶圓正面的環(huán)氧樹脂作為一種支撐,可以在芯片很薄的情況下保護其不易受損,通過系統優(yōu)化,使該工藝達到可以工業(yè)化生產的程度也為將來芯片進一步減薄創(chuàng)造了條件。高鉛焊錫料倒裝粘結下管芯容易出現點膠不穩(wěn)定的問題,通過對點膠過程的細致分析,根據點膠頭的孔徑選擇合理的點膠高度有助于穩(wěn)定工藝效果,較大的孔徑對穩(wěn)定的點膠非常重要。高鉛焊錫料粘結上管芯片設計了框架卡槽來對銅片進行定位,防止銅片旋轉,提高了產品的良品率。清洗工藝研究了市面上比較流行的清洗藥水和清洗參數對產品后續(xù)引線鍵合的影響,指明了優(yōu)化的參數和藥水型號。本文根據上述結構設計和工藝的研究,將優(yōu)化方案整合到整體的工藝流程里,確定了這種新型驅動功率器件模組工藝的制造流程。通過工藝參數優(yōu)化提升了單項工藝穩(wěn)定可重復性,然后采用如上所述的工藝制造了一種新型的驅動電源管理器件模組(DrMOS)模型采用專業(yè)的電子熱分析有限元軟件Flothermal,研究了高密度封裝DrMOS模塊在PCB板上集成典型設計的溫度分布,提出了新型DrMOS模塊應用設計的一些建議。對封裝產品取樣測試表明,樣品在典型功率負載下的溫度分布和熱應力變形均在設計預期和應用允許的范圍之內,功率效率顯著提升,這充分說明利用多種先進封裝技術完成的本項新產品,在體積顯著降低的同時性能得到提升,開發(fā)獲得成功。
[Abstract]:The power chip package package must properly solve the heat dissipation problem, and the stack package should be paid more attention, because the stack makes the heat dissipation area narrow, the heat accumulation phenomenon will be more obvious. There are many reports about this kind of problem. But the products of power device stacking package are not common. Therefore, how to design the structure in the existing technology system, Process reforming and key process improvement to solve the above problems is a subject that must be faced in the development of this kind of new product. This project is developed around a new type of power device module product QFN3.5x5 stacked package technology, which includes two MOSFET power devices core and a control circuit IC chip. It is a stacked package structure that forms a reasonable heat dissipation structure so as to maintain good thermal stability while reducing the volume significantly. The focus is to develop a stack package process, complete module package and key characteristic test. For this reason, the whole structure design of stacked package is established by demonstration, and then the simulation is carried out through Abaqus software. Then, the packaging structure is optimized. Then, in view of the optimized package structure, the package process flow design scheme is put forward to integrate the existing unit process, optimize the key single item technology, form the package package process, complete the module batch production and thermal stress characteristics test. The overall package architecture is the copper lead frame of the main body. A MOSFET power chip is mounted on both sides of the surface, then the control circuit IC chip is stacked above the upper tube core, and then the lead bonding is used to interconnect and seal. The copper sheet with the outstanding thermal conductivity is used as the main structure to better solve the heat export problem of the power chip. The whole process of the packaging process can be divided into two parts. Wafer level pre treatment process module and assembly bonding process module. The wafer level preprocessing technology includes the following main processes: wafer front chemical plating NiAu-- high lead tin balls - reflow soldering - Cleaning - epoxy resin sealing on the front of the wafer -- the front thin exposed lead tin electrode - the back of wafer surface thinning - Ti Ni Ag metal layer. Assembly bonding process The module flow is as follows: using high lead solder paste to bond the pipe chip - using high lead solder to bond tube chip and copper chip - Cleaning - stacked IC chip to copper chip - curing insulating adhesive - lead bonding - plastic seal - back cut, etc. On the basis of the art line, it focuses on the technology of high lead tin ball planting, the plastic sealing process of the epoxy resin in the front of the wafer, the bonding process of the high lead solder material in the pipe chip, the technology of the bonding copper sheet of the high lead solder material on the pipe chip, and the cleaning technology. A special screen is developed to meet the requirements of the product. The thinning of the circular crystal helps to heat the heat quickly, but the thinning operation is easily broken or other breakage, affecting the yield. The epoxy resin on the front of the wafer can be used as a support and can not be easily damaged under the thin chip of the chip. The process can be optimized by system optimization. The degree of industrial production also creates conditions for further thinning of chips in the future. The high lead solder paste chip designed the frame card slot to locate the copper sheet, prevent the copper sheet from rotated and improve the product's good product rate. The cleaning process has studied the influence of the popular cleaning water and cleaning parameters on the following lead bonding of the product, pointing out the optimized parameters and the model of the medicine water. This paper is based on this paper. In the study of the structure design and process, the optimization scheme is integrated into the whole process flow, and the manufacturing process of the new driving power device module is determined. The stability and repeatability of the single process are improved by optimizing the process parameters. Then a new type of power management device is made by the technology described above. The model module (DrMOS) model uses the specialized electronic thermal analysis finite element software Flothermal to study the temperature distribution of the typical design of the high density package DrMOS module on the PCB board, and puts forward some suggestions for the application design of the new DrMOS module. The force deformation is within the range of design expectation and application, and the power efficiency is greatly improved. This fully illustrates the new product completed by various advanced packaging technology. The performance is improved while the volume is significantly reduced, and the development is successful.
【學位授予單位】：上海交通大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN405

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