基于AXI的SoC互聯(lián)結構的設計與驗證
發(fā)布時間：2018-07-17 20:17
【摘要】：隨著集成電路的發(fā)展和半導體工藝的進步,基于IP核復用技術的片上系統(tǒng)(SoC)設計被越來越廣泛的運用于各個領域。針對SoC中IP核的互連,傳統(tǒng)的總線結構顯現(xiàn)出傳輸帶寬低、難以支持并行通信、地址空間有限等問題;IP核通信協(xié)議也常反映出難以實現(xiàn)低延時、高頻率、低功耗和靈活性等缺點。本文研究設計了一種基于AXI協(xié)議的SoC matrix互聯(lián)結構,一方面能夠體現(xiàn)AXI協(xié)議的優(yōu)點,在點對點傳輸時實現(xiàn)低延時、高效率和高吞吐率的特點,另一方面避免了總線結構的一些不足之處,實現(xiàn)N-M并行通信,最后并對設計進行功能驗證。具體工作如下:1.分析AXI傳輸過程與結構特點,并結合系統(tǒng)并行通信的要求,設計出一種針對主設備的多數(shù)據(jù)緩存、針對目標從設備的共享地址多數(shù)據(jù)緩存的拓撲結構,實現(xiàn)IP核與互連架構模塊的基于AXI協(xié)議的outstanding傳輸、亂序訪問及N-M并行通信。2.帶有仲裁配置寄存器,可通過相應的握手協(xié)議對該寄存器進行改寫,使SoC在不同的應用場合下采用可定義的仲裁優(yōu)先級實現(xiàn)更高效的通信。3.設計帶AXI接口的SRAM控制器與AXI2APB Bridge,兩者作為從設備掛載在AXI互連架構上,實現(xiàn)寫操作中地址與數(shù)據(jù)無先后差別的傳輸,并對模塊優(yōu)化。4.搭建UVM驗證平臺對模塊、部件進行功能驗證,編寫UVM中driver、monitor、sequencer、agent、reference model、scoreboard等組成部分,生成帶約束的隨機激勵,并對結果進行自動檢查,采用不同的testcase驗證不同的功能點,并且驗證結果正確。
[Abstract]:With the development of integrated circuits and semiconductor technology, the design of SoC based on IP core multiplexing technology is more and more widely used in various fields. For the interconnection of IP cores in SoC, the traditional bus architecture shows that the transmission bandwidth is low, it is difficult to support parallel communication, the address space is limited and so on, IP core communication protocols often reflect that it is difficult to achieve low delay and high frequency. The disadvantages of low power consumption and flexibility. In this paper, a matrix interconnection architecture based on AXI-based protocol is designed. On the one hand, it can embody the advantages of AXIprotocol and realize the characteristics of low delay, high efficiency and high throughput in point-to-point transmission. On the other hand, it avoids some shortcomings of bus architecture, realizes N-M parallel communication, and verifies the function of the design. The work is as follows: 1. This paper analyzes the characteristics of AXI transmission process and structure, and designs a topology of multi-data cache for main equipment and shared address multi-data cache for target slave device, combined with the requirement of system parallel communication. The implementation of IP core and interconnection architecture module based on AXI-based outstanding transmission, out-of-order access and N-M parallel communication. 2. With the arbitration configuration register, the register can be rewritten by the corresponding handshake protocol, so that SoC can use the defined arbitration priority to achieve more efficient communication. The SRAM controller with AXI interface and the AXI2APB bridge are designed, which are mounted on the AXI interconnection architecture as slave devices to realize the transmission of the address and data in the write operation, and optimize the module. 4. Building a verification platform for modules and components to verify the function of modules and components, writing components such as driver monitor and sequence reference model scoreboard, generating random excitation with constraints, and automatically checking the results, and using different testcase to verify different function points. And verify the results are correct.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN47
本文編號：2130820
[Abstract]:With the development of integrated circuits and semiconductor technology, the design of SoC based on IP core multiplexing technology is more and more widely used in various fields. For the interconnection of IP cores in SoC, the traditional bus architecture shows that the transmission bandwidth is low, it is difficult to support parallel communication, the address space is limited and so on, IP core communication protocols often reflect that it is difficult to achieve low delay and high frequency. The disadvantages of low power consumption and flexibility. In this paper, a matrix interconnection architecture based on AXI-based protocol is designed. On the one hand, it can embody the advantages of AXIprotocol and realize the characteristics of low delay, high efficiency and high throughput in point-to-point transmission. On the other hand, it avoids some shortcomings of bus architecture, realizes N-M parallel communication, and verifies the function of the design. The work is as follows: 1. This paper analyzes the characteristics of AXI transmission process and structure, and designs a topology of multi-data cache for main equipment and shared address multi-data cache for target slave device, combined with the requirement of system parallel communication. The implementation of IP core and interconnection architecture module based on AXI-based outstanding transmission, out-of-order access and N-M parallel communication. 2. With the arbitration configuration register, the register can be rewritten by the corresponding handshake protocol, so that SoC can use the defined arbitration priority to achieve more efficient communication. The SRAM controller with AXI interface and the AXI2APB bridge are designed, which are mounted on the AXI interconnection architecture as slave devices to realize the transmission of the address and data in the write operation, and optimize the module. 4. Building a verification platform for modules and components to verify the function of modules and components, writing components such as driver monitor and sequence reference model scoreboard, generating random excitation with constraints, and automatically checking the results, and using different testcase to verify different function points. And verify the results are correct.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN47
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