發(fā)布時(shí)間：2018-07-08 18:50

  本文選題：壓控振蕩器 + 相位噪聲�。� 參考：《湖南大學(xué)》2015年碩士論文

【摘要】：隨著現(xiàn)代通信技術(shù)的日益發(fā)展,特別是無(wú)線通信技術(shù)的全面推廣,電子通信系統(tǒng)延續(xù)了高性能、低成本、集成化的發(fā)展趨勢(shì),而壓控振蕩器又是無(wú)線通信技術(shù)最核心的部分,電子設(shè)備對(duì)壓控振蕩器的技術(shù)指標(biāo)要求越來(lái)越高。傳統(tǒng)的分立壓控振蕩器功耗高、頻率范圍低且?guī)捳?與集成芯片之間的寄生參數(shù)大,這些都限制了它無(wú)法滿足現(xiàn)代無(wú)線的技術(shù)指標(biāo);而目前集成壓控振蕩器已經(jīng)能夠集成,性能優(yōu)秀,但是與CMOS集成壓控振蕩器相比,有兩個(gè)明顯的不足:一是工藝成本高,如果整個(gè)系統(tǒng)都采用此類工藝(諸如砷化鎵工藝、雙極型工藝、Bi Cmos工藝),將使得產(chǎn)品的造價(jià)成倍的上升,難以實(shí)現(xiàn)批量生產(chǎn);二是使用的不是CMOS工藝,與后端數(shù)字電路不兼容,也就難以進(jìn)行系統(tǒng)級(jí)芯片設(shè)計(jì)(System On Chip)�，F(xiàn)在的客戶都追求小、精、廉的價(jià)值觀念,為了適應(yīng)客戶的需求以及電子技術(shù)的主流發(fā)展趨勢(shì),設(shè)計(jì)一款低相噪、寬頻域、低功耗的CMOS工藝的集成壓控振蕩器,易于進(jìn)行系統(tǒng)級(jí)芯片設(shè)計(jì),大幅提高整個(gè)產(chǎn)品的性能,使產(chǎn)品做到真正的物美價(jià)廉,已是電子通信技術(shù)發(fā)展的必然走向�；谠O(shè)計(jì)壓控振蕩器的基本理論,結(jié)合國(guó)內(nèi)外的研究現(xiàn)狀,設(shè)計(jì)出了一款低相位噪聲、寬頻域CMOS集成壓控振蕩器。論文首先簡(jiǎn)單的介紹了壓控振蕩器的發(fā)展?fàn)顩r,并提出了相應(yīng)的一些技術(shù)指標(biāo)和要求,然后對(duì)集成壓控振蕩器的設(shè)計(jì)做出了分析,這些分析主要包括集成壓控振蕩器常用結(jié)構(gòu)的特點(diǎn)、拓?fù)涞倪x擇及LC振蕩器中變?nèi)莨芎推想姼械脑O(shè)計(jì)要求等等。論文重點(diǎn)介紹了低相位噪聲和寬頻域調(diào)諧的壓控振蕩器的設(shè)計(jì),對(duì)平面螺旋電感進(jìn)行了優(yōu)化和對(duì)MOS變?nèi)莨苓M(jìn)行了參數(shù)設(shè)計(jì),通過(guò)建立壓控振蕩器的小信號(hào)等效模式,確立了設(shè)計(jì)參數(shù)。論文對(duì)壓控振蕩器的其他相關(guān)電路模塊也進(jìn)行了簡(jiǎn)單的分析。主要工作成果有:諧振回路無(wú)源器件的片上實(shí)現(xiàn),對(duì)無(wú)源器件的閃爍噪聲進(jìn)行重點(diǎn)優(yōu)化,降噪技術(shù)為二次諧波諧振技術(shù)和感性壓控端技術(shù)。電路設(shè)計(jì)采用SMIC 0.18μm CMOS射頻工藝,利用Cadence軟件的Spectre RF工具仿真,仿真結(jié)果為:中心頻率為2.00 GHz,輸出頻率為1.85 GHz到2.15 GHz,調(diào)諧范圍為15%,相位噪聲為-120 d Bc/@1MHz,靜態(tài)功耗為0.72 m W。完全達(dá)到了設(shè)計(jì)要求。
[Abstract]:With the development of modern communication technology, especially the popularization of wireless communication technology, electronic communication system continues the development trend of high performance, low cost and integration, and voltage controlled oscillator is the core part of wireless communication technology. The technical requirements of VCO are becoming higher and higher in electronic equipment. The traditional discrete voltage controlled oscillator has high power consumption, low frequency range and narrow bandwidth, and large parasitic parameters with the integrated chip, which limit it to meet the technical requirements of modern wireless, but the integrated voltage controlled oscillator has been able to integrate. Performance is excellent, but there are two obvious disadvantages compared to CMOS integrated VCO: one is the high cost of the process, if the whole system uses such a process (such as gallium arsenide process, Gallium arsenide process), The bipolar process (Bi CMOS process) will double the cost of the product and make it difficult to realize batch production. Second, it is difficult to design system on Chip because it is not a CMOS process and is incompatible with the back end digital circuit. In order to meet the needs of customers and the mainstream trend of electronic technology, we design an integrated VCO with low phase noise, wide frequency domain and low power consumption in CMOS process. It is an inevitable trend of the development of electronic communication technology that it is easy to design system-level chips, greatly improve the performance of the whole product, and make the products really good and cheap. Based on the basic theory of designing VCO, a low phase noise, broadband CMOS integrated VCO is designed. Firstly, the development of VCO is briefly introduced, and some technical specifications and requirements are put forward, then the design of integrated VCO is analyzed. These analyses mainly include the characteristics of the common structure of the integrated VCO, the choice of topology and the design requirements of the varactor and on-chip inductor in the LC oscillator. This paper mainly introduces the design of VCO with low phase noise and wide frequency domain tuning, optimizes the planar spiral inductor and designs the parameters of MOS varactor. The small signal equivalent mode of VCO is established. The design parameters are established. The other circuit modules of VCO are also analyzed in this paper. The main results are as follows: the on-chip realization of the passive devices in the resonant circuit, the optimization of the scintillation noise of the passive devices, the second harmonic resonance technology and the inductive voltage-controlled terminal technology are used to reduce the noise. The circuit is designed in SMIC 0.18 渭 m CMOS RF process. The simulation results are as follows: the center frequency is 2.00 GHz, the output frequency is 1.85 GHz to 2.15 GHz, the tuning range is 15x, the phase noise is -120 d Bc / r -1MHz, and the static power consumption is 0.72 MW. Fully meet the design requirements.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN752

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

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本文編號(hào)：2108417