發(fā)布時(shí)間：2018-07-02 09:08

  本文選題：無線傳感器網(wǎng)絡(luò) + 鎖相環(huán)��； 參考：《東南大學(xué)》2015年碩士論文

【摘要】：隨著無線通信技術(shù)的不斷發(fā)展,無線傳感器網(wǎng)絡(luò)(Wireless Sensor Network, WSN)將會(huì)逐漸成熟,其在信息感知領(lǐng)域的巨大價(jià)值使其備受國際科技界的關(guān)注。隨著無線傳感器網(wǎng)絡(luò)的發(fā)展,對射頻收發(fā)芯片的要求越來越高。本文研究的內(nèi)容是無線傳感網(wǎng)鎖相環(huán)頻率綜合器中的小數(shù)分頻器和自動(dòng)頻率校正AFC電路。本文設(shè)計(jì)了應(yīng)用于WSN射頻頻率綜合器中的二分頻器、三分頻器、可編程分頻器、EA調(diào)制器和自動(dòng)頻率校準(zhǔn)電路,所有電路基于TSMC0.18μm CMOS工藝,工作電壓為1V。其中二分頻器采用平行電流開關(guān)源極耦合邏輯結(jié)構(gòu)；三分頻器采用雙沿觸發(fā)器環(huán)形連接,保證輸出占空比為50%;可編程分頻器采用雙模預(yù)分頻器和PS計(jì)數(shù)器結(jié)構(gòu),實(shí)現(xiàn)速率與功耗的平衡,PS計(jì)數(shù)器采用全定制設(shè)計(jì)方法,提高工作頻率使得可使用分頻器較小的預(yù)分頻器,減小整個(gè)可編程分頻器的最小連續(xù)分頻比：ΣA調(diào)制器采用改進(jìn)的MASH 1-1-1結(jié)構(gòu),由三個(gè)一階誤差反饋調(diào)制器(Error Feedback Modulator, EFM)級聯(lián)構(gòu)成,并在相鄰兩個(gè)EFM之間增加一個(gè)前饋連接,最終達(dá)到減小小數(shù)雜散的目的；自動(dòng)頻率校準(zhǔn)電路采用開環(huán)工作的頻率檢測方案,在工作時(shí)間和電路復(fù)雜度之間取得平衡,符合本系統(tǒng)要求。后仿真結(jié)果表明,在電源電壓為1V,溫度為27。tt工藝角下,二分頻器工作頻率范圍為4～8GHz,輸入信號頻率為5GHz時(shí)對應(yīng)的輸出信號正交誤差約0.310,正交性良好；三分頻器的工作頻率范圍為0.5～4.5GHz,占空比為50%；可編程分頻器的工作頻率范圍為1.0～6.5GHz,在最高工作頻率時(shí)功耗為3.99mW;∑△調(diào)制器輸入20位分頻比的小數(shù)位,輸出3位動(dòng)態(tài)分頻比,工作正常,與可編程分頻器聯(lián)合工作正確實(shí)現(xiàn)小數(shù)分頻,工作頻率范圍為1.0-6.5GHz,分頻比范圍為186.72-221.76,頻率分辨率為24Hz,核心功耗不超過4.8mmW。本文設(shè)計(jì)的可編程分頻器進(jìn)行了流片,得到最終測試結(jié)果為：芯片面積為0.675mm X 0.378mm,可編程分頻器工作頻率范圍為0.5～6.0GHz,在6.0GHz下的功耗為3.48mW。測試結(jié)果滿足設(shè)計(jì)指標(biāo)。本文所設(shè)計(jì)的各個(gè)模塊滿足WSN系統(tǒng)的要求,并且具有低功耗的特點(diǎn),預(yù)期可以應(yīng)用到WSN核心芯片中。
[Abstract]:With the continuous development of wireless communication technology, Wireless Sensor Network (WSN) will gradually mature, and its great value in the field of information perception has attracted the attention of the international science and technology community. With the development of wireless sensor networks, RF transceiver chips are required more and more. The content of this paper is the fractional frequency divider and the automatic frequency correction AFC circuit in the phase locked loop frequency synthesizer of the wireless sensor network. In this paper, two divider, three frequency divider, programmable frequency divider EA modulator and automatic frequency calibration circuit used in WSN RF frequency synthesizer are designed. All circuits are based on TSMC 0.18 渭 m CMOS technology and the working voltage is 1V. The two-frequency divider adopts parallel current switch source polar coupling logic structure, the three-frequency divider adopts double-edge trigger annular connection to ensure the output duty cycle is 50, the programmable frequency divider adopts dual-mode predivider and PS counter structure. The balanced PS counter, which realizes speed and power consumption, adopts a fully customized design method, which increases the working frequency so that a predivider with smaller frequency divider can be used. Reducing the minimum continuous frequency ratio of the whole programmable frequency divider: 危 A modulator adopts an improved MASH1-1-1 structure, which consists of three first-order error feedback modulator (EFM) cascades, and adds a feedforward connection between two adjacent EFM. The automatic frequency calibration circuit uses open-loop frequency detection scheme to achieve a balance between working time and circuit complexity, which meets the requirements of the system. The simulation results show that when the power supply voltage is 1V and the temperature is 27.tt process angle, the frequency range of the frequency divider is 4g / 8GHz, and the quadrature error of the output signal is about 0.310 when the input signal frequency is 5GHz, and the orthogonality is good. The operating frequency range of the three divider is 0.5 ~ 4.5GHz, the duty cycle is 50GHz, the working frequency range of the programmable divider is 1.0 ~ 6.5GHz, and the power consumption is 3.99mW at the highest operating frequency. The 鈭，

本文編號：2089630