本文選題：SoC設(shè)計(jì) + 時(shí)鐘復(fù)用�。� 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：隨著半導(dǎo)體產(chǎn)業(yè)的快速發(fā)展和集成電路工藝尺寸的縮小,SoC(System on Chip)芯片設(shè)計(jì)包含的內(nèi)容越來(lái)越廣泛,集成度也越來(lái)越高,功耗問題成了如今芯片設(shè)計(jì)中性能、封裝、制冷和設(shè)備安全的制約因素;而且,隨著以電池為主要供電方式的便攜式和小型化設(shè)備需求的增加,電池技術(shù)的發(fā)展滯后于集成電路的快速發(fā)展也促進(jìn)了低功耗設(shè)計(jì)需求。因此,系統(tǒng)芯片的低功耗設(shè)計(jì)是人們?cè)谠u(píng)估芯片面積、成本以及性能的同時(shí),需要綜合考慮的重要問題。在當(dāng)前的集成電路系統(tǒng)設(shè)計(jì)中,運(yùn)用廣泛而且有效的低功耗技術(shù)有:多閾值電壓技術(shù)、電源關(guān)斷技術(shù)、時(shí)鐘關(guān)斷技術(shù)、網(wǎng)表優(yōu)化技術(shù)以及多電壓供電技術(shù)等。芯片正常工作的時(shí)候,動(dòng)態(tài)功耗占總功耗的90%以上,時(shí)鐘路徑上的動(dòng)態(tài)功耗占系統(tǒng)總功耗的40%左右。因此,本論文針對(duì)一個(gè)設(shè)計(jì)項(xiàng)目進(jìn)行分析,優(yōu)先確定并使用了時(shí)鐘關(guān)斷技術(shù)、網(wǎng)表優(yōu)化技術(shù)以及多電壓供電技術(shù),但仍不能完成本設(shè)計(jì)項(xiàng)目對(duì)低功耗設(shè)計(jì)更高標(biāo)準(zhǔn)的要求。最后根據(jù)對(duì)設(shè)計(jì)項(xiàng)目功能結(jié)構(gòu)的具體分析得出:通過(guò)時(shí)鐘復(fù)用的方法用多位觸發(fā)器代替一位觸發(fā)器可以有效地降低時(shí)鐘路徑上的動(dòng)態(tài)功耗、減少單元面積,達(dá)到了低功耗設(shè)計(jì)標(biāo)準(zhǔn)。本論文主要優(yōu)化設(shè)計(jì)了多位觸發(fā)器,并有效的應(yīng)用到了實(shí)際設(shè)計(jì)項(xiàng)目中,且在不違反新工藝的設(shè)計(jì)規(guī)則下,主要進(jìn)行了以下工作:首先,使用時(shí)鐘復(fù)用的方法分析設(shè)計(jì)了多位觸發(fā)器的電路,并設(shè)計(jì)出完整的GDSII(Graphic Database System II)版圖。從版圖中抽取器件之間的寄生參數(shù)(包括電阻和電容),分析了多位觸發(fā)器的性能并比較了多位觸發(fā)器單元的優(yōu)勢(shì)。根據(jù)多位觸發(fā)器的結(jié)構(gòu),定制出包含有時(shí)序信息和功耗信息的單元庫(kù)。其次,對(duì)于常用的芯片設(shè)計(jì)流程,工具并不能準(zhǔn)確的應(yīng)用多位觸發(fā)器,基于對(duì)數(shù)據(jù)路徑的分析,在網(wǎng)表綜合階段通過(guò)路徑映射的方法將多位觸發(fā)器加入到芯片的邏輯結(jié)構(gòu)中,在布局布線階段修正掉設(shè)計(jì)規(guī)則的違例,在最終分析階段對(duì)芯片進(jìn)行邏輯分析和功耗時(shí)序分析。最后,在系統(tǒng)設(shè)計(jì)中通過(guò)使用自主設(shè)計(jì)的多位觸發(fā)器并結(jié)合其他的低功耗技術(shù),從而將功耗降低了36%,達(dá)到了最初要求的35%的標(biāo)準(zhǔn)。本論文的研究已取得了很好的成果,并應(yīng)用到實(shí)際的設(shè)計(jì)項(xiàng)目中。
[Abstract]:With the rapid development of semiconductor industry and the reduction of integrated circuit process size, SoC (system on Chip) chip design contains more and more contents, and the integration level is becoming higher and higher. With the increasing demand for portable and miniaturized devices with battery as the main mode of power supply, the development of battery technology lags behind the rapid development of integrated circuits, which also promotes the demand for low-power design. Therefore, the low power design of the system chip is an important issue to be considered when evaluating the chip area, cost and performance. In the current integrated circuit system design, the widely used and effective low-power technologies include multi-threshold voltage technology, power off technology, clock turn off technology, network meter optimization technology and multi-voltage power supply technology. When the chip works normally, the dynamic power consumption accounts for more than 90% of the total power consumption, and the dynamic power consumption on the clock path accounts for about 40% of the total power consumption of the system. Therefore, this paper analyzes a design project, prioritizes and uses clock turn-off technology, network table optimization technology and multi-voltage power supply technology, but still can not meet the design project for a higher standard of low-power design. Finally, according to the concrete analysis of the function structure of the design project, it is concluded that the dynamic power consumption on the clock path can be effectively reduced and the cell area can be reduced by using multi-bit trigger instead of one bit trigger by the method of clock multiplexing. The design standard of low power consumption is reached. This paper mainly optimizes the design of multi-bit trigger, and applies it to the actual design project effectively, and under the condition of not violating the design rules of the new process, the main work is as follows: first, The circuit of multi-bit trigger is analyzed and designed by using clock multiplexing method, and a complete layout of GDSII (graphic Database system II) is designed. The parasitic parameters (including resistors and capacitors) between devices are extracted from the layout. The performance of multi-bit flip-flop is analyzed and the advantages of multi-bit flip-flop cells are compared. According to the structure of multi-bit trigger, the cell library which contains timing information and power information is customized. Secondly, for the commonly used chip design flow, the tool can not use the multi-bit trigger accurately. Based on the analysis of the data path, the multi-bit trigger is added to the logic structure of the chip through the path mapping method in the synthesis stage of the network table. In the layout and routing phase, the design rule violation is corrected, and the chip logic analysis and power sequence analysis are carried out in the final analysis stage. Finally, by using self-designed multi-bit flip-flop and other low-power technologies in the system design, the power consumption is reduced by 36%, and the standard of 35% is reached. The research of this paper has obtained very good result, and applied to the actual design project.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN47

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