本文選題：時(shí)序收斂 + 關(guān)鍵路徑　； 參考：《國防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：集成電路的快速發(fā)展,使得芯片的集成度更高、性能更加優(yōu)異,而芯片的時(shí)序收斂卻變得更加困難。本文以YHFT-DX芯片中L_unit部件的物理設(shè)計(jì)為研究對象,研究了如何有效優(yōu)化關(guān)鍵路徑,達(dá)到時(shí)序收斂的目的,減少芯片的上市時(shí)間(time-to-market)。YHFT-DX芯片采用40nm工藝設(shè)計(jì),要求在最差工作條件(worst case)下時(shí)鐘頻率達(dá)到1GHz。L_unit部件作為YHFT-DX芯片的重要部件之一,結(jié)構(gòu)設(shè)計(jì)相對復(fù)雜,在經(jīng)過多次迭代優(yōu)化設(shè)計(jì)后,仍存在一些時(shí)序違反的關(guān)鍵路徑,為快速消除這些關(guān)鍵路徑,本文采用延時(shí)更低的脈沖鎖存器來替換這些路徑上的寄存器。本文首先分析標(biāo)準(zhǔn)單元庫中的寄存器的版圖結(jié)構(gòu),再根據(jù)脈沖鎖存器的基本原理,采用全定制設(shè)計(jì)流程設(shè)計(jì)出了實(shí)驗(yàn)所需的脈沖鎖存器。在通過后仿真驗(yàn)證后,與同功能的標(biāo)準(zhǔn)單元對比,脈沖鎖存器的延時(shí)減小51.9%。然后,根據(jù)脈沖鎖存器的結(jié)構(gòu)特點(diǎn)將一位寬脈沖鎖存器成組實(shí)現(xiàn)了水平結(jié)構(gòu)的多位寬脈沖鎖存器,并從減小電壓降(IR-drop)的角度分析,設(shè)計(jì)出了垂直結(jié)構(gòu)的多位寬脈沖鎖存器。這兩種結(jié)構(gòu)的多位寬脈沖鎖存器在獲得延時(shí)減小的同時(shí),與同功能的標(biāo)準(zhǔn)單元對比,三、四、五位寬脈沖鎖存器的單位功耗和單位面積都優(yōu)于標(biāo)準(zhǔn)單元。并通過實(shí)驗(yàn)證明了多位寬脈沖鎖存器在輸出負(fù)載為30飛法(FF)、分別使用M3~M7作為互連線時(shí),30um的互連線延時(shí)為2ps左右。根據(jù)造成時(shí)序違反的因素,提出了采用全定制設(shè)計(jì)的一位寬脈沖鎖存器替換關(guān)鍵路徑上寄存器的優(yōu)化方案及算法,并將優(yōu)化算法轉(zhuǎn)化成自動(dòng)處理腳本。同時(shí),分析了在不同階段進(jìn)行替換的優(yōu)點(diǎn),最終實(shí)驗(yàn)結(jié)果表明:在布局(place)階段進(jìn)行替換優(yōu)化,以寄存器到寄存器(Reg2reg)路徑的時(shí)序違反數(shù)量(Violating Paths)和最差時(shí)序違反(WNS)為衡量標(biāo)準(zhǔn),關(guān)鍵路徑減少了99.45%,整體電路時(shí)序性能提升12%左右。最后,根據(jù)多位寬脈沖鎖存器的優(yōu)勢和特點(diǎn),提出了采用多位寬脈沖鎖存器優(yōu)化關(guān)鍵路徑的方案,依托前兩章實(shí)驗(yàn)所獲得的結(jié)果,解決了方案中出現(xiàn)的問題。并同樣將優(yōu)化方案轉(zhuǎn)化成優(yōu)化算法和自動(dòng)處理腳本,大大提高了算法的實(shí)用性和工作效率。實(shí)驗(yàn)證明,在邊長為30um的矩形內(nèi),使用水平結(jié)構(gòu)的三位寬脈沖鎖存器,在place階段替換該區(qū)域內(nèi)關(guān)鍵路徑上的寄存器,所獲得的效果最好。以Reg2reg路徑的Violating Paths和WNS為衡量標(biāo)準(zhǔn),關(guān)鍵路徑減少了99%,整體電路時(shí)序性能提升11.4%,整體功耗降低2.5%,芯片密度降低4.4%。經(jīng)多次實(shí)驗(yàn)證明,采用脈沖鎖存器能夠有效的優(yōu)化關(guān)鍵路徑,加速芯片的時(shí)序收斂,并能在一定程度上降低芯片的整體功耗和密度。
[Abstract]:With the rapid development of integrated circuits, the integration and performance of the chips become higher and better, but the timing convergence of the chips becomes more difficult. In this paper, the physical design of the LHFT-DX part in YHFT-DX chip is taken as the research object, and how to optimize the critical path effectively, to achieve the purpose of timing convergence, and to reduce the time to market (time-to-market) of the chip. YHFT-DX chip is designed by 40nm process. As one of the most important components of YHFT-DX chip, the clock frequency of 1GHz 路L\ + (worst case) is required under the worst working conditions. The structure design is relatively complex. After several iterations, there are still some critical paths of timing violation. In order to eliminate these critical paths quickly, a lower delay pulse latch is used to replace the registers on these paths. In this paper, the layout of registers in the standard cell library is analyzed, and then, according to the basic principle of pulse latch, the pulse latch is designed according to the whole custom design flow. The delay of the pulse latch is reduced by 51.9 compared with the standard unit of the same function after the post-simulation verification. Then, according to the structural characteristics of the pulse latch, a multi-bit wide pulse latch with horizontal structure is implemented in groups, and the vertical multi-bit wide pulse latch is designed from the angle of reducing the voltage drop. Compared with the standard cells of the same function, the three, four, and five bits wide pulse latch have better unit power consumption and unit area than the standard cells. It is proved by experiments that the interconnection delay of M3M7 is about 2ps when the output load is 30 flight (FF) and M3M7 is used as the interconnect line respectively. According to the causes of timing violation, an optimized scheme and algorithm for replacing registers in critical path by a fully customized design of a wide pulse latch is proposed, and the optimization algorithm is transformed into an automatic processing script. At the same time, the advantages of substitution in different stages are analyzed. The final experimental results show that the replacement optimization is carried out in the layout (place) phase, and the measurements are based on the number of sequential violations and the worst sequential violations in the register to register path. The critical path is reduced by 99.45, and the timing performance of the whole circuit is improved by about 12%. Finally, according to the advantages and characteristics of the multi-bit wide pulse latch, a scheme of using multi-bit wide pulse latch to optimize the critical path is proposed. Based on the experimental results obtained in the previous two chapters, the problems in the scheme are solved. The optimization scheme is also transformed into optimization algorithm and automatic processing script, which greatly improves the practicability and working efficiency of the algorithm. The experimental results show that in the rectangle with the length of 30um, the use of a horizontal three-bit wide pulse latch to replace the registers on the critical path in the place stage is the best. By using Reg2reg path's Violating paths and WNS as the standard, the critical path is reduced by 99 percent, the timing performance of the whole circuit is improved by 11.4g, the overall power consumption is reduced by 2.5 and the chip density is reduced by 4.4. It has been proved by many experiments that the pulse latch can effectively optimize the critical path, accelerate the timing convergence of the chip, and reduce the overall power consumption and density of the chip to a certain extent.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN40

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