發(fā)布時(shí)間：2018-06-27 22:36

  本文選題：全并行模數(shù)轉(zhuǎn)換器 + 逐次逼近型模數(shù)轉(zhuǎn)換器�。� 參考：《合肥工業(yè)大學(xué)》2017年碩士論文

【摘要】：隨著CMOS半導(dǎo)體工藝的迅速發(fā)展,數(shù)字信號(hào)處理技術(shù)得到了很大提高。相對(duì)于模擬信號(hào),數(shù)字信號(hào)有著更高的可靠性、簡(jiǎn)便性以及靈活性等優(yōu)點(diǎn),因此數(shù)字信號(hào)處理已成為現(xiàn)代信號(hào)處理的主流方式。模數(shù)轉(zhuǎn)換器(Analog-to-Digital,ADC)作為連接模擬信號(hào)和數(shù)字信號(hào)的紐帶,需要先將自然界中的模擬信號(hào)轉(zhuǎn)換成數(shù)字信號(hào)后,系統(tǒng)才能利用數(shù)字信號(hào)處理的方式處理模擬信號(hào)。因此,人們對(duì)ADC的需求越來(lái)越強(qiáng)烈,同時(shí)對(duì)其研究也日益受到關(guān)注。逐次逼近型(successive approximation register,SAR) ADC因其結(jié)構(gòu)簡(jiǎn)單、功耗低、面積小等優(yōu)點(diǎn)而獲得廣泛運(yùn)用�；趥鹘y(tǒng)結(jié)構(gòu)的N比特SAR ADC每完成一次轉(zhuǎn)換都需要進(jìn)行N次比較,而每次的比較速度又受限于電容型數(shù)模轉(zhuǎn)換器(Digital to Analog Converter,DAC)的建立時(shí)間和邏輯控制電路的傳遞延遲。因此,傳統(tǒng)結(jié)構(gòu)的這種缺陷阻礙了 SARADC向高速高精度領(lǐng)域的發(fā)展。全并行模數(shù)轉(zhuǎn)換器(Flash ADC)由于結(jié)構(gòu)和工作原理相對(duì)簡(jiǎn)單,因此其轉(zhuǎn)換速度非常高。但是隨著ADC位數(shù)的增加,其面積和功耗成指數(shù)型增長(zhǎng),因此給ADC的高精度設(shè)計(jì)帶來(lái)了挑戰(zhàn)。全并行—逐次逼近混合型模數(shù)轉(zhuǎn)換器(Flash-SARADC)是一種將Flash ADC和SARADC各自的優(yōu)點(diǎn)相結(jié)合的新型ADC結(jié)構(gòu),由于其在面積、速度、功耗以及精度方面具有較好的折中,因此得到了廣泛的研究。本文首先對(duì)Flash-SAR ADC的工作原理和系統(tǒng)結(jié)構(gòu)進(jìn)行了闡述,同時(shí)詳細(xì)分析了其結(jié)構(gòu)中存在的非理想因素,并提出了相應(yīng)的解決方案。接著,本文在對(duì)現(xiàn)有的開關(guān)策略進(jìn)行分析和對(duì)比的基礎(chǔ)上,提出了一種高位電容跳過與復(fù)用的開關(guān)策略,從而大幅度優(yōu)化了電荷再分配型DAC的動(dòng)態(tài)功耗和面積。相對(duì)于MCS開關(guān)策略,提出的開關(guān)策略使電容陣列所需的電容總數(shù)減小一半,電平切換功耗降低81.22%。然后,詳細(xì)介紹了關(guān)鍵電路的設(shè)計(jì),并給出了系統(tǒng)仿真結(jié)果。最后,本文采用SMIC0.18μmCMOS混合信號(hào)工藝設(shè)計(jì)了一款10位100MS/s Flash-SAR混合型ADC。所設(shè)計(jì)的ADC采用“3+8”的兩極流水線結(jié)構(gòu),最后通過冗余位數(shù)字校準(zhǔn)電路得到10位的量化精度。電路仿真結(jié)果表明:當(dāng)采樣信號(hào)的頻率為100MS/s,輸入信號(hào)的頻率為48.14453125MHz的滿幅正弦差分信號(hào)時(shí)的輸出信號(hào)的無(wú)雜散波動(dòng)態(tài)范圍(SFDR)為75.879dB、信號(hào)噪聲失真比(SNDR)為61.37dB、有效位數(shù)(ENOB)位9.902位;當(dāng)采樣頻率為l00MS/s,輸入信號(hào)頻率為1.07421875MHz,工藝角為FF時(shí),ADC的SFDR為78.669dB,SNDR為61.839dB,ENOB為9.980 bit;當(dāng)工藝角為TT時(shí),ADC的SFDR為 76.201dB,SNDR為61.15dB,ENOB為9.865bit;當(dāng)工藝角為 SS 時(shí),ADC 的 SFDR 為 76.937dB, SNDR 為 60.594dB, ENOB 為 9.773 bit。提出的Flash-SAR ADC在1.8V電源電壓和Nyquist輸入信號(hào)下,芯片功耗為 2.41mW,品質(zhì)因數(shù)(Figure of merit, FOM)為 25.19fJ/conversion-step。
[Abstract]:With the rapid development of CMOS semiconductor technology, digital signal processing technology has been greatly improved. Compared with analog signal, digital signal has higher reliability, simplicity and flexibility, so digital signal processing has become the mainstream of modern signal processing. As the link between analog signal and digital signal, Analog-to-digital converter (ADC) needs to convert the analog signal into digital signal before the system can process the analog signal by digital signal processing. Therefore, the demand for ADC is becoming more and more intense, and the research on ADC has been paid more and more attention. Successive approximation (successive approximation register (successive approximation) ADC is widely used because of its simple structure, low power consumption and small area. The traditional N-bit Analog ADCs need to be compared for N times for each conversion, and the speed of each comparison is limited by the time of establishment of the digital to Analog converter and the transfer delay of the logic control circuit. Therefore, this defect of traditional structure hinders the development of SARADC to high speed and high precision. Full parallel analog-to-digital converter (Flash ADC) is very fast because of its simple structure and working principle. However, with the increase of ADC bits, its area and power consumption increase exponentially, which brings challenges to the high precision design of ADC. Full-parallel-successive approximation hybrid analog-to-digital converter (Flash-SARADC) is a new ADC structure which combines the advantages of Flash ADC and SARADC. Due to its good compromise in area, speed, power consumption and precision, it has been widely studied. In this paper, the working principle and system structure of Flash-SAR ADC are described, and the non-ideal factors in the structure are analyzed in detail, and the corresponding solutions are put forward. Then, based on the analysis and comparison of the existing switching strategies, this paper proposes a switching strategy with high capacitance skipping and multiplexing, which greatly optimizes the dynamic power consumption and area of charge redistribution DAC. Compared with the MCS switching strategy, the proposed switching strategy reduces the total capacitance required by half and the switching power consumption by 81.22. Then, the design of the key circuit is introduced in detail, and the simulation results are given. Finally, a 10-bit 100MS / s Flash-SAR hybrid ADCC is designed using SMIC 0.18 渭 m CMOS mixed signal technology. The designed ADC adopts a "38" two-pole pipeline structure. Finally, the quantization accuracy of 10 bits is obtained by the redundant bit digital calibration circuit. The circuit simulation results show that when the sampling signal frequency is 100ms / s and the input signal frequency is 48.14453125MHz, the output signal has a non-spurious wave dynamic range (SFDR) of 75.879dB, a signal-to-noise distortion ratio (SNDR) of 61.37dB and a significant bit (ENOB) of 9.902 bits. When the sampling frequency is 100 Ms / s, the input signal frequency is 1.07421875 MHz and the process angle is FF, the SFDR of the ADC is 78.669 dBN, SNDR is 61.839 dB ENOB is 9.980 bit, when the processing angle is TT, the SFDR of the ADC is 76.201dBSNDR 61.15 dB ENOB is 9.865 bit. when the processing angle is SS, the SFDR of the ADC is 76.937 dB, the SNDR is 60.594dB, and the ENOB is 9.773 bit. when the processing angle is SS, the SFDR of the ADC is 76.937dB, the SNDR is 60.594dB, and the ENOB is 9.773 bit. Under 1.8V supply voltage and Nyquist input signal, the proposed Flash-SAR ADC has a power consumption of 2.41 MW and a figure of merit (FOM) of 25.19fJ / conversion-step.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792

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本文編號(hào)：2075506