本文選題：模數(shù)轉(zhuǎn)換器 + 時(shí)間交織��； 參考：《華中科技大學(xué)》2015年碩士論文

【摘要】：隨著先進(jìn)的數(shù)字系統(tǒng)遠(yuǎn)遠(yuǎn)超越模擬電路,尤其是制造工藝線移向納米級(jí)別后,最近十幾年對(duì)高速、高精度、低功耗的模數(shù)轉(zhuǎn)換器(ADC)的需求越來(lái)越迫切。流水線型模數(shù)轉(zhuǎn)換器是從中頻采樣到高頻采樣并且具有高精度的典型結(jié)構(gòu)。然而在深亞微米,低電源電壓下設(shè)計(jì)一個(gè)高增益高帶寬低功耗的運(yùn)算放大器是比較困難的。為了避免這種限制,好幾個(gè)流水線型模數(shù)轉(zhuǎn)換器利用時(shí)間交織技術(shù)合并成一個(gè)整體的模數(shù)轉(zhuǎn)換器的構(gòu)想被提了出來(lái)�？傮w來(lái)說(shuō),時(shí)間交織流水線型模數(shù)轉(zhuǎn)換器是復(fù)雜結(jié)構(gòu)和能量利用率之間折中選擇。基于以上考慮,本文采用SMIC 0.13um CMOS工藝設(shè)計(jì)了一款12位200MSPS的時(shí)間交織流水線型模數(shù)轉(zhuǎn)換器。采用時(shí)間交織、流水線、運(yùn)放共享等技術(shù),既提高了速度和精度也節(jié)省了功耗。同時(shí)為了減小時(shí)序扭曲對(duì)時(shí)間交織流水線模數(shù)轉(zhuǎn)換器性能的影響,提出了一種對(duì)時(shí)序扭曲不敏感的采樣保持電路。本文首先對(duì)模數(shù)轉(zhuǎn)換器的工作原理和典型的結(jié)構(gòu)做了介紹;然后從系統(tǒng)結(jié)構(gòu)、流水線型模數(shù)轉(zhuǎn)換器和子模塊的設(shè)計(jì)方面分析了實(shí)現(xiàn)12位200MSPS模數(shù)轉(zhuǎn)換器的方案;最后給出了本文要求的高速高精度模數(shù)轉(zhuǎn)換器的電路設(shè)計(jì)和仿真。仿真結(jié)果表明在采樣速率為200MSPS,模擬輸入信號(hào)頻率為60MHz時(shí)無(wú)雜散動(dòng)態(tài)范圍可以達(dá)到88.8dB,信噪失真比為73.2dB,而功耗為107mW。
[Abstract]:With the advanced digital system far beyond analog circuits, especially after the manufacturing process line moves to nanometer level, the demand for high speed, high precision, low power ADC (ADC) is becoming more and more urgent in the last decade. Pipeline A / D converter is a typical structure with high precision from if sampling to high frequency sampling. However, it is difficult to design an operational amplifier with high gain, high bandwidth and low power consumption at deep submicron and low power supply voltage. In order to avoid this limitation, several pipelined analog-to-digital converters have been proposed to merge into a whole analog-to-digital converter using time interleaving technology. In general, time interleaving pipelined A / D converters are a trade-off between complex structures and energy utilization. Based on the above considerations, a 12 bit 200 MSPS time interleaving pipeline A / D converter is designed using SMIC 0.13um CMOS technology. Time interleaving, pipelining and operational amplifier sharing are used to improve speed and precision and save power consumption. In order to reduce the influence of time sequence distortion on the performance of time interleaving pipeline A / D converter, a sampling and holding circuit which is not sensitive to time sequence distortion is proposed. In this paper, the working principle and typical structure of A / D converter are introduced firstly, and then the scheme of 12 bit 200 MSPS ADC is analyzed from the aspects of system structure, pipeline ADC and sub-module design. At last, the circuit design and simulation of high-speed and high-precision A-D converter are given. The simulation results show that when the sampling rate is 200MSPS and the analog input signal frequency is 60MHz, the spurious dynamic range can reach 88.8dB, the signal-to-noise ratio is 73.2dB, and the power consumption is 107mW.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792

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