本文選題：DDS + ROM��； 參考：《河北大學(xué)》2015年碩士論文

【摘要】：在鐵電材料研究中,鐵電材料的極化和反轉(zhuǎn)時(shí)需要較高的電壓,因此要求具有高輸出電壓的信號(hào)源,目前市場上常規(guī)信號(hào)源輸出電壓一般為5Vpp,這顯然不能滿足實(shí)驗(yàn)室研究使用,針對(duì)于此問題,論文提出一種基于FPGA利用直接頻率合成(DDS)技術(shù)開發(fā)任意波形高壓源的方法。高壓信號(hào)源的設(shè)計(jì)主要分為兩個(gè)部分,一個(gè)是FPGA的任意波形發(fā)生器的開發(fā),一部分是對(duì)任意信號(hào)升壓并放大輸出功率。任意波形發(fā)生器的設(shè)計(jì)是基于直接頻率合成(DDS)技術(shù)在可編程邏輯器件上設(shè)計(jì)實(shí)現(xiàn)。論文在介紹DDS開發(fā)技術(shù)的基礎(chǔ)上,給出了本系統(tǒng)在FPGA上總體設(shè)計(jì)方案,采用Verilog HDL硬件描述語言完成了DDS波形發(fā)生模塊設(shè)計(jì),結(jié)合設(shè)計(jì)中遇到ROM資源不夠的問題,對(duì)DDS ROM壓縮技術(shù)的應(yīng)用與實(shí)現(xiàn)進(jìn)行了重點(diǎn)研究與介紹,本設(shè)計(jì)分別針對(duì)正弦波、三角波對(duì)稱性,鋸齒波的單調(diào)性,方波的幅值只有0和1的特點(diǎn)做了不同的優(yōu)化壓縮設(shè)計(jì),最終壓縮比達(dá)到16:3,而硬件電路僅僅增加了一個(gè)計(jì)數(shù)器和一個(gè)反向器,解決了設(shè)計(jì)時(shí)FPGA ROM資源不夠的問題。任意波形發(fā)生器的控制單元采用了SOPC技術(shù),利用Nios II軟核處理器實(shí)現(xiàn)對(duì)DDS波形發(fā)生模塊、LCD液晶屏的控制,以及對(duì)鍵盤的控制信號(hào)的采集,在控制單元的設(shè)計(jì)上,論文重點(diǎn)分析了Nios II系統(tǒng)的HAL開發(fā)環(huán)境,給出了對(duì)LCD和鍵盤控制的流程圖,并用C語言設(shè)計(jì)了相關(guān)程序。信號(hào)升壓模塊采用了浮動(dòng)電壓源技術(shù),將普通運(yùn)算放大器的輸出電壓從±15V升高至±20V,最終設(shè)計(jì)了運(yùn)算放大器驅(qū)動(dòng)的甲乙類功率放大器實(shí)現(xiàn)了功率放大的同時(shí)解決了甲乙類放大器的交越失真問題。最終測試結(jié)果表明,系統(tǒng)實(shí)現(xiàn)了頻率0-1Mhz可調(diào)的正弦波、三角波、鋸齒波及占空比可調(diào)的方波波形輸出,信號(hào)理論分辨率可達(dá)0.023Hz,實(shí)測最小頻率小于10Hz,輸出峰峰值電壓最高可達(dá)40Vpp。
[Abstract]:In the study of ferroelectric materials, the polarization and reversal of ferroelectric materials require high voltage, so the signal source with high output voltage is required. The current output voltage of the conventional signal source in the market is generally 5Vpp, which is obviously unable to be used in laboratory research. In this paper, a kind of FPGA based direct frequency synthesis (DD) is proposed in this paper. S) technology to develop arbitrary waveform high voltage source. The design of high voltage signal source is divided into two parts, one is the development of arbitrary waveform generator of FPGA, the other is to boost and amplify the output power of any signal. The design of arbitrary waveform generator is based on the design of direct frequency synthesis (DDS) technology on programmable logic devices. On the basis of introducing the DDS development technology, the paper gives the overall design scheme of this system on the FPGA, and uses the Verilog HDL hardware description language to complete the design of DDS waveform generation module. Combined with the problem of insufficient ROM resources in the design, the application and implementation of the DDS ROM compression technology are emphatically studied and introduced, and the design is divided into this design. The pin on the sine wave, triangle wave symmetry, the monotonicity of the sawtooth wave, the Fang Bo's amplitude only 0 and 1 characteristics do different optimal compression design, the final compression ratio reaches 16:3, and the hardware circuit only adds a counter and a reverse device, which solves the problem of insufficient FPGA ROM resources in the design. The unit uses the SOPC technology, uses the Nios II soft core processor to realize the DDS waveform generation module, the LCD LCD screen control, and the acquisition of the control signal of the keyboard. In the design of the control unit, the paper focuses on the HAL development environment of the Nios II system, gives the flow chart of the LCD and keyboard control, and designs the correlation with the C language. The signal boost module uses the floating voltage source technology to increase the output voltage of the ordinary operational amplifier from + 15V to + 20V. Finally, a class a class B power amplifier driven by an operational amplifier has been designed to achieve the power amplification and the problem of the crossings of the class a class B amplifier. The final test results show that the system is implemented. The frequency 0-1Mhz adjustable sine wave, triangular wave, sawtooth wave and square wave output with adjustable occupied space ratio, the theoretical resolution of the signal can reach 0.023Hz, the measured minimum frequency is less than 10Hz, and the maximum peak and peak voltage of the output can reach 40Vpp.
【學(xué)位授予單位】：河北大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN741;TN791

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