本文選題：單粒子效應(yīng) + 軟錯(cuò)誤��； 參考：《合肥工業(yè)大學(xué)》2015年碩士論文

【摘要】：隨著集成電路工藝水平的不斷提高,CMOS晶體管工藝尺寸的不斷縮小,以及工作電壓不斷降低,使得電路節(jié)點(diǎn)電容隨之減少,導(dǎo)致CMOS電路越發(fā)容易受到輻射效應(yīng)引起的軟錯(cuò)誤的影響。單粒子效應(yīng)分為兩類,一類是發(fā)生在時(shí)序單元中的單粒子翻轉(zhuǎn)(SEU),另一類是發(fā)生在組合邏輯電路中的單粒子瞬態(tài)(SET)。當(dāng)粒子轟擊組合邏輯的敏感節(jié)點(diǎn),會出現(xiàn)瞬態(tài)故障脈沖,該脈沖被稱為單粒子瞬態(tài)(SET)脈沖。當(dāng)粒子轟擊到存儲單元的內(nèi)部節(jié)點(diǎn),會產(chǎn)生沉積電荷,當(dāng)達(dá)到臨界電荷時(shí),會導(dǎo)致存儲值發(fā)生翻轉(zhuǎn),該情況被稱為單粒子翻轉(zhuǎn)(SEU)。SET脈沖可能會沿著數(shù)據(jù)路徑傳播并被下游的時(shí)序單元所捕捉,發(fā)生軟錯(cuò)誤。但是由于組合邏輯單元的邏輯屏蔽效應(yīng)、電氣屏蔽效應(yīng)和時(shí)序存儲單元的時(shí)窗屏蔽效應(yīng)的影響,SET故障脈沖可能會被屏蔽。另一方面,近期的實(shí)驗(yàn)數(shù)據(jù)表明,容SEU技術(shù)已經(jīng)成為納米工藝下抗輻射加固鎖存器設(shè)計(jì)的一個(gè)重要問題。對于高密度的存儲器件,通常采用低成本的糾錯(cuò)碼技術(shù)進(jìn)行防護(hù)。因此,在一般的應(yīng)用中,存儲單元已不是防護(hù)的重點(diǎn)。加固技術(shù)研究主要集中在鎖存器和觸發(fā)器的領(lǐng)域。基于上述情況,本論文主要研究工作如下：(1)學(xué)習(xí)研究了由空間輻射引起的單粒子效應(yīng),探討其產(chǎn)生環(huán)境,作用機(jī)理,以及對集成電路的影響效果等方面。并對現(xiàn)有的解決單粒子效應(yīng)的方法進(jìn)行了分析和歸類,比較了它們各自的優(yōu)缺點(diǎn)。(2)在納米工藝水平下,提出一種適用于低功耗電路的高速抗輻射加固鎖存器(SRHL)結(jié)構(gòu),針對鎖存器更容易受到高能粒子轟擊產(chǎn)生軟錯(cuò)誤的情形,本文采用由12個(gè)晶體管構(gòu)成的反饋冗余矩陣及一個(gè)保護(hù)門C單元結(jié)構(gòu),其中反饋冗余矩陣的每個(gè)晶體管或節(jié)點(diǎn)的狀態(tài)均由其相鄰晶體管或節(jié)點(diǎn)決定。SRHL鎖存器的內(nèi)部節(jié)點(diǎn)和輸出節(jié)點(diǎn)在受到高能粒子轟擊產(chǎn)生瞬態(tài)故障后均具有快速自恢復(fù)能力,不會影響鎖存器正常工作。相比其他的鎖存器加固方案,我們提出的鎖存器在延遲,功耗等方面有著性能優(yōu)勢并且在應(yīng)用范圍上更加廣泛。針對45nm工藝,使用SPICE仿真工具進(jìn)行仿真的實(shí)驗(yàn)結(jié)果表明,SRHL鎖存器比以往的軟錯(cuò)誤加固鎖存器有著面積,延遲,功耗上的優(yōu)勢。
[Abstract]:With the continuous improvement of integrated circuit technology level, the process size of CMOS transistor is shrinking and the working voltage is decreasing, which makes the capacitance of circuit node decrease. CMOS circuits are more vulnerable to soft errors caused by radiation effects. Single particle effect can be divided into two categories, one is single particle transition (SEU) which occurs in sequential unit, and the other is single particle transient (set) in combinational logic circuits. When particles bombard sensitive nodes of combinational logic, transient fault pulses occur, which are called single particle transient (set) pulses. When the particle bombardes the internal node of the memory cell, it generates a deposited charge, and when the critical charge is reached, it causes the storage value to flip. This situation is called single particle flip (SEU). Set pulse may propagate along the data path and be captured by the downstream time series unit, resulting in soft errors. But due to the logic shielding effect of combinational logic unit, the effect of electrical shielding effect and time window shielding effect of sequential memory cell, the set fault pulse may be shielded. On the other hand, recent experimental data show that the capacitive SEU technology has become an important issue in the design of anti-radiation reinforcement latch in nanotechnology. For high density memory devices, low-cost error-correcting codes are usually used to protect them. Therefore, in general applications, memory cells are no longer the focus of protection. The research of reinforcement technology is mainly concentrated in the field of latch and flip-flop. Based on the above, the main work of this thesis is as follows: (1) the single particle effect caused by space radiation is studied, and the environment, the mechanism and the effect on the integrated circuit are discussed. The existing methods to solve the single particle effect are analyzed and classified, and their respective advantages and disadvantages are compared. (2) at the level of nanotechnology, a high speed radiation resistant strengthened latch (SRHL) structure for low power circuits is proposed. In this paper, a feedback redundancy matrix composed of 12 transistors and a guard gate C cell structure are used to solve the problem that latch is more vulnerable to soft errors caused by high energy particle bombardment. The state of each transistor or node of the feedback redundancy matrix is determined by its adjacent transistors or nodes. The internal nodes and output nodes of the SRHL latch have the ability of fast self-recovery after being bombarded by high-energy particles to produce transient faults. Does not affect the latch to work properly. Compared with other latch reinforcement schemes, the proposed latch has many advantages in delay and power consumption, and has a wider range of applications. For the 45nm process, the simulation results using spice simulation tool show that the latch has the advantages of area, delay and power consumption compared with the previous soft error strengthened latch.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402

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