本文選題：SPICE模型 + 高壓VDMOS模型��； 參考：《杭州電子科技大學(xué)》2015年碩士論文

【摘要】：功率VDMOS(Vertical Conduction Double-Diffused Metal Oxide Semicondu ctor)(垂直雙擴(kuò)散場效應(yīng)晶體管)器件是功率電子的主流產(chǎn)品之一。憑借其輸入阻抗高、安全工作區(qū)寬、開關(guān)速度快和熱穩(wěn)定性好等很多特點(diǎn),VDMOS廣泛地應(yīng)用于開關(guān)電源、電機(jī)驅(qū)動(dòng)、節(jié)能燈和汽車電子部件等各種領(lǐng)域。我國在VDM OS器件研究方面已經(jīng)取得了不少進(jìn)展,但是還不夠成熟,而且我國很多VDMO S產(chǎn)品需要進(jìn)口,于是,對功率VDMOS器件的特性探究及其模型建立和模型優(yōu)化存在著非常重要的意義。論文選取士蘭微電子近期推出了新一代高壓MOSFET產(chǎn)品——S-RinTM系列高壓VDMOS,應(yīng)用于AC-DC功率電源,DC-DC轉(zhuǎn)換器以及PWM馬達(dá)驅(qū)動(dòng)等領(lǐng)域。本文簡要介紹了VDMOS應(yīng)用和發(fā)展前景以及模型研究的意義,概述了模型相關(guān)理論,包括SPICE模型及其發(fā)展,還有MET模型的特點(diǎn)和主要考慮的器件物理機(jī)制,接著介紹器件測試系統(tǒng)和模型提取軟件及較詳細(xì)全面的模型提取步驟,然后介紹功率VDMOS的結(jié)構(gòu)發(fā)展以及分析了其直流特性、熱溫度特性和動(dòng)態(tài)電容特性,最后對VDMOS進(jìn)行直流測試和動(dòng)態(tài)電容測試,包括輸出特性曲線、轉(zhuǎn)移特性曲線(I-V曲線)以及動(dòng)態(tài)電容曲線(C-V曲線),選擇模型提取軟件對VDMOS建模。過程中發(fā)現(xiàn)初始MET模型由于主要是面向橫向結(jié)構(gòu)MOSFET器件,所以無法很好地對VDMOS器件進(jìn)行表征。由此,在MET模型的基礎(chǔ)上,在VDMOS的漏極添加一個(gè)受柵極電壓跟漏極電壓控制的電阻,很好地?cái)M合VDMOS測試數(shù)據(jù),提高模型精度,同時(shí)論文還在MET模型的VA(Verilog-A)模型文件中進(jìn)行一些改動(dòng),在Verilog-A代碼中修改原始方程,添加個(gè)別主要用于擬合線性區(qū)和飽和區(qū)的參數(shù),從而使得優(yōu)化后的MET模型仿真曲線與VDMOS實(shí)際IV特性相符。對于CV曲線擬合的解決辦法,論文主要是對實(shí)測數(shù)據(jù)進(jìn)行一個(gè)分段函數(shù)的近似,然后把分段函數(shù)用子電路的形式表達(dá)出來,最后通過Cadence仿真得到的CV曲線擬合度較高,典型器件Id-Vg曲線誤差Err:MAX=100%|RMS=16.96%,Cgd-Vgd曲線誤差Err:MAX=22.43%|RMS=3.001%。
[Abstract]:Power VDMOSU Vertical production Double-Diffused Metal Oxide Semicondu (Vertical double Diffusion Field effect Transistor) devices are one of the mainstream products of power electronics. VDMOS is widely used in many fields, such as switching power supply, motor drive, energy saving lamp and automotive electronic parts, because of its high input impedance, wide safe working area, fast switching speed and good thermal stability. China has made a lot of progress in the research of VDM OS devices, but it is not mature enough, and many VDMO S products need to be imported in our country. It is of great significance to explore the characteristics of power VDMOS devices, model establishment and model optimization. In this paper, a new generation of high voltage MOSFET products, S-RinTM series high voltage VDMOSs, has been developed by Shirawuer Microelectronics, which has been used in AC-DC power supply, DC-DC converters and PWM motor drivers. This paper briefly introduces the application and development prospects of VDMOS and the significance of model research, and summarizes the related theories of the model, including spice model and its development, as well as the characteristics of met model and the main device physics mechanism considered. Then it introduces the device testing system, model extraction software and the detailed and comprehensive model extraction steps, then introduces the structure development of power VDMOS and analyzes its DC characteristics, thermal temperature characteristics and dynamic capacitance characteristics. Finally, the DC and dynamic capacitance of VDMOS are tested, including output characteristic curve, transfer characteristic curve and I-V curve) and dynamic capacitance curve. Model extraction software is selected to model VDMOS. It was found that the initial met model could not be used to characterize the VDMOS devices because it was mainly transversely oriented MOSFET devices. Therefore, on the basis of met model, a resistance controlled by gate voltage and drain voltage is added to the drain of VDMOS, which can fit the test data of VDMOS well and improve the accuracy of the model. At the same time, some changes have been made in the VAAGA-VAilog-Amodel file of met model, and the original equation has been modified in Verilog-A code, and some parameters which are mainly used to fit the linear region and saturation region have been added. The simulation curve of the optimized met model is in accordance with the actual IV characteristics of VDMOS. For the solution of CV curve fitting, the paper mainly carries on a piecewise function approximation to the measured data, and then expresses the piecewise function in the form of subcircuit. Finally, the fitting degree of CV curve obtained by Cadence simulation is higher. The error of Id-Vg curve Err: MAX1 is 100% RMS16.96 and the error of Cgd-Vgd curve Err: MAXD 22.43% RMS3.001.
【學(xué)位授予單位】：杭州電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386

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