本文選題：模數(shù)轉(zhuǎn)換器 + 逐次逼近型��； 參考：《南京郵電大學(xué)》2017年碩士論文

【摘要】：數(shù)字電路的飛速發(fā)展以及高效、廉價(jià)的優(yōu)勢(shì)使其在集成電路領(lǐng)域占據(jù)非常重要的位置�，F(xiàn)實(shí)中很多信號(hào)都是未經(jīng)處理的模擬信號(hào),因此模數(shù)轉(zhuǎn)換器作為模擬信號(hào)轉(zhuǎn)換成數(shù)字信號(hào)的重要器件,一直備受關(guān)注。逐次逼近模數(shù)轉(zhuǎn)換器具有電路結(jié)構(gòu)簡(jiǎn)單,面積小的優(yōu)勢(shì)并且速度和精度適中,模擬電路部分較少,能與快速發(fā)展的CMOS工藝相兼容,在低功耗嵌入式系統(tǒng)以及可攜帶設(shè)備中有著廣泛的應(yīng)用。本文實(shí)現(xiàn)了一種1MS/s的8位逐次逼近模數(shù)轉(zhuǎn)換器電路,數(shù)模轉(zhuǎn)換器采用單端結(jié)構(gòu),可以減少開(kāi)關(guān)數(shù)量和降低功耗,同時(shí)使用一個(gè)dummy電容陣列來(lái)彌補(bǔ)時(shí)鐘饋通和比較器失調(diào)電壓。比較器是帶預(yù)放大級(jí)的動(dòng)態(tài)比較器,在調(diào)節(jié)輸入失調(diào)電壓的同時(shí)可有效隔離輸入和輸出。數(shù)字時(shí)序采用改進(jìn)型位片式單元(Bit-Slice Unit,BSU)模塊實(shí)現(xiàn)SAR邏輯,有效減少M(fèi)OS管數(shù)量的同時(shí)減少功耗。仿真結(jié)果表明,在0.18μm CMOS工藝,采樣率為1MS/s的條件下,當(dāng)輸入信號(hào)頻率為5.86KHz時(shí),SNR為50.1dB,SNDR為49.3d B,SFDR為68.6dB,ENOB為7.89bit,功耗為16.5μW,FOM值為65.8fJ/step。此外,本文還提出了一個(gè)基于信號(hào)自相關(guān)性的低功耗逐次逼近型模數(shù)轉(zhuǎn)換器結(jié)構(gòu)。使用比較器比較前后兩次采樣信號(hào)的差值,如果比較結(jié)果小于某一閾值則進(jìn)行較少位數(shù)的A/D轉(zhuǎn)換,從而降低A/D轉(zhuǎn)換功耗,并通過(guò)仿真驗(yàn)證其可行性。
[Abstract]:With the rapid development of digital circuits and the advantages of high efficiency and low cost, they occupy a very important position in the field of integrated circuits. In reality, many signals are unprocessed analog signals, so analog-to-digital converters, as an important device for the conversion of analog signals to digital signals, have attracted much attention. The successive approximation A / D converter has the advantages of simple circuit structure, small area, moderate speed and accuracy, less analog circuits, and compatible with the rapidly developing CMOS process. It is widely used in low power embedded systems and portable devices. In this paper, an 8-bit successive approximation A / D converter circuit with 1MS / s is implemented. It uses a single terminal structure to reduce the number of switches and power consumption, and uses an dummy capacitor array to compensate for clock feedthrough and comparator offset voltage. The comparator is a dynamic comparator with preamplifier stage, which can effectively isolate input and output while adjusting input offset voltage. The improved Bit-slice Unit-BSUU module is used to realize SAR logic, which can reduce the number of MOS transistors and reduce the power consumption. The simulation results show that in 0.18 渭 m CMOS process with a sampling rate of 1 MS / s, when the input frequency is 5.86 kHz, the SNR is 50.1 dB / s and the SNDR is 49.3 dB / s, the ENOB is 6.89 bit and the power consumption is 16.5 渭 WFOM = 65.8 fJ / s. In addition, a low power successive approximation analog-to-digital converter architecture based on signal autocorrelation is proposed. The comparator is used to compare the difference between the two sampling signals. If the comparison result is less than a certain threshold, the power consumption of the A- / D conversion is reduced, and the feasibility is verified by simulation.
【學(xué)位授予單位】：南京郵電大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792

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本文編號(hào)：2037567