本文選題：超寬帶 + 自偏置　； 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：隨著信息化時代的到來,人們對通信的需求越來越高,為了提高通信效率、降低通信成本、加強通信安全性,超寬帶技術(shù)(Ultra WideBand,UWB)應(yīng)運而生。而超寬帶低噪聲放大器作為無線接收機前端的重要模塊,其性能直接影響著超寬帶接受機的整體性能。本文的研究對象為超寬帶低噪聲放大器。在系統(tǒng)分析了近年來全球的超寬帶低噪聲放大器研究狀況后,對超寬帶低噪聲放大器的實現(xiàn)原理進行了分析,并將目前主流的幾種超寬帶低噪聲放大器拓?fù)浣Y(jié)構(gòu)進行了詳細(xì)的分析以及對比,總結(jié)其優(yōu)點以及缺點。然后,在現(xiàn)有結(jié)構(gòu)的基礎(chǔ)上,提出一種新型的全對稱自偏置低功耗的超寬帶低噪聲放大器電路,并進行設(shè)計仿真得到結(jié)果以及版圖。最后,在前文設(shè)計的基礎(chǔ)上,又提出了一種結(jié)合人工神經(jīng)網(wǎng)絡(luò)工作特點,對超寬帶低噪聲放大器進行進一步優(yōu)化的設(shè)計。本次設(shè)計,主要結(jié)合了近年來超寬帶低噪聲放大器的主流設(shè)計架構(gòu),通過將可以實現(xiàn)帶寬展寬的自偏置電阻負(fù)反饋匹配電路和用以實現(xiàn)良好阻抗匹配電感源極負(fù)反饋電路結(jié)合得到了電路的第一級結(jié)構(gòu)即輸入匹配級電路,在獲得足夠增益帶寬的同時也滿足了輸入阻抗的匹配條件;而為了使低噪聲放大器得到足夠的增益尤其是高頻增益,又進一步設(shè)計了第二級高頻增益放大電路來使得總體電路的增益滿足條件,并利用電感串聯(lián)峰化技術(shù)將兩級電路級聯(lián)在一起以保證獲得足夠的工作帶寬。論文的第三章最后給出了本次超寬帶低噪聲放大器的仿真結(jié)果,其工作帶寬為1GHz-10.6GHz,在此工作帶寬內(nèi),電路增益為15.6-18dB,噪聲系數(shù)NF為2.4dB-3.9dB,并實現(xiàn)了不錯的輸入阻抗匹配(S11-10dB),而整個電路的功耗也較低,電路的總功耗僅僅為9.75mW。同目前的同類研究對比,該電路的帶寬、增益、噪聲都有著一定的優(yōu)勢。為了進一步提高超寬帶低噪聲放大器的性能,本文第四章提出了一種利用人工神經(jīng)網(wǎng)絡(luò)的記憶能力以及學(xué)習(xí)能力來對超寬帶低噪聲放大器性能進行優(yōu)化的方法,并給出了實際案例。
[Abstract]:With the arrival of the information age, the demand for communication becomes higher and higher. In order to improve communication efficiency, reduce communication cost and enhance communication security, Ultra wide Band (UWB) technology emerges as the times require. As an important module of wireless receiver, UWB LNA has a direct impact on the overall performance of UWB receiver. The research object of this paper is UWB LNA. After systematically analyzing the research status of UWB LNA in recent years, the realization principle of UWB LNA is analyzed. The main topology of UWB LNA is analyzed and compared in detail, and its advantages and disadvantages are summarized. Then, based on the existing structure, a novel full-symmetric self-biased low-power UWB low-noise amplifier circuit is proposed, and the simulation results and layout are obtained. Finally, on the basis of the previous design, a further optimization design of UWB LNA is proposed, which combines the characteristics of artificial neural network (Ann). This design mainly combines the mainstream design architecture of UWB LNA in recent years. By combining the self-bias resistor negative feedback matching circuit which can realize the bandwidth broadening and the good impedance matching inductance source negative feedback circuit, the first stage structure of the circuit, namely the input matching stage circuit, is obtained. In order to obtain sufficient gain bandwidth and satisfy the matching condition of input impedance, in order to obtain sufficient gain, especially high frequency gain, Furthermore, the second stage high frequency gain amplifier circuit is designed to satisfy the gain condition of the whole circuit, and the two stage circuits are cascaded together by the inductance series peaking technique to ensure the sufficient working bandwidth. In the third chapter, the simulation results of the UWB LNA are given. The bandwidth of the UWB LNA is 1 GHz ~ 10.6 GHz. The gain of the circuit is 15.6-18dB, the noise coefficient NF is 2.4dB-3.9dB, and a good input impedance matching S11-10dBN is realized. The power consumption of the whole circuit is also low, and the total power consumption of the circuit is only 9.75mW. Compared with the current research, this circuit has some advantages in bandwidth, gain and noise. In order to further improve the performance of UWB LNA, the fourth chapter of this paper proposes a method to optimize the performance of UWB LNA by using the memory ability and learning ability of artificial neural network. A practical case is given.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN722.3

【參考文獻】

相關(guān)期刊論文 前8條

1 解放;羅闖;;CMOS模擬集成電路版圖設(shè)計[J];微處理機;2012年03期

2 趙萌;李雪;韓波;高建軍;;高速跨阻放大器設(shè)計綜述[J];電子器件;2009年03期

3 姚芳;李秋利;;淺談CMOS模擬集成電路版圖設(shè)計的器件匹配方法[J];集成電路通訊;2008年04期

4 吳岳婷;張潤曦;沈懌皓;陳元盈;周灝;賴宗聲;;433MHz ASK接收機射頻前端版圖設(shè)計[J];微電子學(xué);2007年06期

5 劉抒民;田立卿;;使用負(fù)反饋技術(shù)設(shè)計寬帶低噪聲放大器[J];遙測遙控;2007年03期

6 金善子;;模擬電路版圖設(shè)計中的匹配藝術(shù)[J];中國集成電路;2006年12期

7 朱大奇;人工神經(jīng)網(wǎng)絡(luò)研究現(xiàn)狀及其展望[J];江南大學(xué)學(xué)報;2004年01期

8 陳國良，韓文廷;人工神經(jīng)網(wǎng)絡(luò)理論研究進展[J];電子學(xué)報;1996年02期

相關(guān)碩士學(xué)位論文 前4條

1 萬力濤;超寬帶低噪聲放大器的設(shè)計[D];北京交通大學(xué);2013年

2 高艷花;0.18um CMOS工藝低噪聲放大器的電路及版圖設(shè)計[D];復(fù)旦大學(xué);2011年

3 劉白梅;2.4GHz低功耗無線接收機中低噪聲放大器與混頻器研究[D];湖南大學(xué);2010年

4 關(guān)赫;適用于無線局域網(wǎng)的CMOS低噪聲放大器設(shè)計[D];西安電子科技大學(xué);2009年

，

本文編號：2031682