發(fā)布時(shí)間：2018-06-13 20:03

  本文選題：邏輯綜合 + 低功耗　； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著數(shù)字集成電路產(chǎn)業(yè)的迅猛發(fā)展,集成電路后端設(shè)計(jì)質(zhì)量逐漸成為制約芯片良品率和生產(chǎn)成本的重要因素;隨著集成電路工藝尺寸的不斷縮小,集成電路芯片的應(yīng)用領(lǐng)域不斷擴(kuò)大,目前在智能電子、可穿戴設(shè)備和醫(yī)學(xué)上都有很廣泛的應(yīng)用。這些領(lǐng)域的應(yīng)用使得數(shù)字IC芯片不斷向低功耗的方向發(fā)展。在保證芯片性能的情況下,如何將功耗降至最低逐漸成為當(dāng)前集成電路設(shè)計(jì)的重點(diǎn)。在無線數(shù)字通信技術(shù)大發(fā)展的背景下,短距離無線數(shù)傳技術(shù)由于具有功耗低、面積小、成本低及實(shí)現(xiàn)簡單等優(yōu)點(diǎn),已經(jīng)在社會生活的方方面面都得到了應(yīng)用。本文根據(jù)課題組的科研項(xiàng)目,完成了一款基于短距離無線數(shù)傳的基帶芯片的后端設(shè)計(jì),介紹了芯片后端實(shí)現(xiàn)的具體過程,并對在后端實(shí)現(xiàn)過程中遇到的問題以及筆者對后端流程的理解進(jìn)行了詳細(xì)的說明和深入的分析。本文著重進(jìn)行了以下幾個(gè)方面的工作:(1)介紹了邏輯綜合原理和邏輯綜合過程,并詳細(xì)介紹了綜合階段的低功耗設(shè)計(jì)方法——門控時(shí)鐘綜合技術(shù)。應(yīng)用門控時(shí)鐘綜合技術(shù)對短距離無線數(shù)傳基帶芯片進(jìn)行綜合,將綜合后的功耗從52m W降低至38mW,功耗降低了27%。(2)總結(jié)了電路設(shè)計(jì)的時(shí)序要求,對靜態(tài)時(shí)序分析(STA)原理進(jìn)行了詳細(xì)介紹,簡單說明了STA所用的工具以及STA工具的使用方法。并給出了存在違例的路徑的人工處理方法,成功的修正了后端工具分析中出現(xiàn)的時(shí)序違例問題。(3)對后端設(shè)計(jì)流程和版圖設(shè)計(jì)工具進(jìn)行了介紹,并使用Astro完成了短距離無線數(shù)傳基帶芯片的版圖設(shè)計(jì),包括芯片面積、電源的規(guī)劃、時(shí)鐘樹綜合、布局工作和布線工作,并簡單介紹了工藝天線效應(yīng)產(chǎn)生的原因及解決方法,修正了版圖設(shè)計(jì)時(shí)出現(xiàn)的工藝天線效應(yīng)。對版圖設(shè)計(jì)后的網(wǎng)表和寄生參數(shù)文件進(jìn)行靜態(tài)時(shí)序分析,發(fā)現(xiàn)問題并修改網(wǎng)表,然后再修改的網(wǎng)表基礎(chǔ)上用ECO方法修正了版圖。最終版圖面積為1.87mm×2.39mm。(4)簡單介紹了形式驗(yàn)證原理、版圖的物理設(shè)計(jì)要求。對短距離無線數(shù)傳基帶芯片的最終版圖網(wǎng)表與RTL級網(wǎng)表做了形式驗(yàn)證;采用Calibre對最終的版圖做了DRC和LVS,以確保流片的質(zhì)量。(5)完成了流片后的裸片封裝工作,并對芯片進(jìn)行了功能測試,最終芯片滿足了設(shè)計(jì)要求。本文圍繞上述工作,對集成電路后端設(shè)計(jì)過程中的原理性知識、工具的運(yùn)用和實(shí)際的操作方法等方面進(jìn)行了全面的介紹。
[Abstract]:With the rapid development of the digital integrated circuit industry, the design quality of the back end of the integrated circuit has gradually become an important factor that restricts the rate of good products and the production cost of the chip, and with the continuous reduction of the process size of the integrated circuit, IC chips are widely used in smart electronics, wearable devices and medicine. The applications of these fields make the digital IC chip develop to the direction of low power consumption. In order to ensure the performance of the chip, how to minimize the power consumption has gradually become the focus of the current IC design. With the rapid development of wireless digital communication technology, short-range wireless data transmission technology has been applied in all aspects of social life because of its advantages of low power consumption, small area, low cost and simple implementation. In this paper, according to the research project of the research group, a backend design of the baseband chip based on short-range wireless data transmission is completed, and the process of realizing the back-end of the chip is introduced. The problems encountered in the process of back-end implementation and the author's understanding of back-end flow are explained and analyzed in detail. This paper focuses on the following aspects: 1) introduces the principle of logic synthesis and the process of logic synthesis, and introduces in detail the low power consumption design method-gating clock synthesis technology in the synthesis stage. By using the gating clock synthesis technology to synthesize the short distance wireless digital baseband chip, the power consumption is reduced from 52m W to 38 MW, and the power consumption is reduced by 27%.) the timing requirements of the circuit design are summarized. The principle of static time sequence analysis (STAA) is introduced in detail. The tools used in STA and the usage method of STA tools are briefly described. The manual processing method of the illegal path is given, and the time sequence violation problem in the analysis of back-end tools is corrected successfully.) the back-end design flow and layout design tools are introduced. The layout design of short-range wireless digital baseband chip is completed by using Astro, including chip area, power source planning, clock tree synthesis, layout work and wiring work. Fixed the effect of craft antenna in layout design. The static time sequence analysis of the net table and parasitic parameter file after layout design is carried out, the problem is found and the net table is modified, and then the layout is corrected by eco method on the basis of the modified net table. The final layout area is 1.87mm 脳 2.39 mm. 4) the principle of formal verification and the physical design requirements of layout are briefly introduced. The final layout table and RTL level network table of short range wireless digital baseband chip are formally verified, and the final layout is made by calibre to ensure the quality of streaming chip. Finally, the chip meets the design requirements. In this paper, the principle knowledge, the application of tools and the practical operation methods in the design process of integrated circuit back-end are introduced in detail.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402

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本文編號：2015244