本文選題：逐次逼近型ADC + 低功耗　； 參考：《國防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：逐次逼近型(SAR)ADC由于其結(jié)構(gòu)簡單、功耗低、易集成等優(yōu)點,廣泛應(yīng)用于傳感網(wǎng)絡(luò)、生物芯片等低功耗領(lǐng)域。SAR ADC中的功耗主要來源于三部分:DAC電容陣列、數(shù)字控制邏輯以及比較器部分。本文以設(shè)計一款10bit200KSPS超低功耗SARADC為目標(biāo),從比較器、DAC電容陣列兩方面提出降低功耗的優(yōu)化方法�；�10bit超低功耗SAR ADC的應(yīng)用需求,本文提出一種基于二進(jìn)制加權(quán)電容DAC陣列的動態(tài)比較器失調(diào)校準(zhǔn)技術(shù),并基于65納米CMOS工藝設(shè)計實現(xiàn)了一款低功耗低失調(diào)動態(tài)比較器。基于版圖數(shù)據(jù)的模擬仿真結(jié)果表明,在1.2V的工作電壓下,該校準(zhǔn)技術(shù)可以將失調(diào)電壓降低至0.25mV以內(nèi),功耗為0.33μW,功耗開銷增大57%。雖然功耗略有增大,但這樣的開銷是值得的。此外,本文提出一種帶錯誤補(bǔ)償機(jī)制的兩級電容開關(guān)時序方案,并基于65納米CMOS工藝設(shè)計實現(xiàn)了兩款SAR ADC,一種基于Switchback開關(guān)時序方案,一種基于兩級電容開關(guān)時序方案,通過版圖數(shù)據(jù)的模擬仿真結(jié)果對兩款SAR ADC性能做比較,仿真結(jié)果顯示SAR ADC的平均轉(zhuǎn)換功耗降低35.6%,有效位數(shù)增大1.7%,說明帶錯誤補(bǔ)償機(jī)制的兩級電容開關(guān)時序在保證性能(如有效位數(shù))的基礎(chǔ)上可以有效降低SAR ADC整體功耗。
[Abstract]:Because of its simple structure, low power consumption and easy integration, successive approximation ADC is widely used in sensor networks, biochips and other low-power fields. The power consumption in SAR ADC mainly comes from three parts: DAC capacitive array. Digital control logic and comparator section. Aiming at the design of a 10bit 200KSPS ultra-low power SARADC, this paper proposes an optimization method to reduce power consumption from two aspects of comparator DAC capacitor array. Based on the application requirement of 10bit ultra-low power 10bit, this paper presents a dynamic comparator offset calibration technique based on binary weighted capacitive DAC array, and implements a low power low offset dynamic comparator based on 65 nm CMOS process design. The simulation results based on layout data show that the proposed calibration technique can reduce the offset voltage to less than 0.25 MV, and the power consumption is 0.33 渭 W, and the power consumption is increased by 57%. Although the power consumption is slightly increased, the cost is worth it. In addition, a two-stage capacitor switch timing scheme with error compensation mechanism is proposed, and two SAR ADCs are implemented based on 65 nm CMOS process, one is based on switch timing scheme, the other is based on two-stage capacitor switch timing scheme. The performance of the two SAR ADC is compared by the simulation results of the layout data. The simulation results show that the average conversion power consumption of SAR ADC is reduced by 35.6and the effective bit number is increased by 1.7. the results show that the two-stage capacitor switch sequence with error compensation mechanism can effectively reduce the overall power consumption of SAR ADC on the basis of ensuring the performance (such as effective bit number).
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 周文婷;李章全;;SAR A/D轉(zhuǎn)換器中電容失配問題的分析[J];微電子學(xué);2007年02期

相關(guān)博士學(xué)位論文 前1條

1 佟星元;納米級CMOS逐次逼近A/D轉(zhuǎn)換器設(shè)計研究與實現(xiàn)[D];西安電子科技大學(xué);2011年

相關(guān)碩士學(xué)位論文 前1條

1 張詩娟;12位逐次逼近型A/D轉(zhuǎn)換器的設(shè)計[D];華中科技大學(xué);2005年

，

本文編號：2009739