本文選題：CMOS工藝 + 包絡跟蹤技術(shù)��； 參考：《電子科技大學》2017年碩士論文

【摘要】：隨著通信技術(shù)的進一步發(fā)展,無線通訊設備將會越來越復雜,高效率的使用能源不僅能夠延長電池的使用壽命,而且也會大大減少電子儀器的散熱,提高儀器的可靠性。目前,包絡跟蹤技術(shù)由于其電路結(jié)構(gòu)簡單,易于集成以及提高系統(tǒng)效率效果明顯等特點成為國內(nèi)外研究的熱點,本文對包絡跟蹤技術(shù)進行了詳細的研究,并給出了數(shù)種提高效率的新結(jié)構(gòu),這些結(jié)構(gòu)對于提高電路系統(tǒng)的效率具有非常重要的意義。首先,幾種常見的包絡放大器結(jié)構(gòu)被一一簡介,并分別對比了它們的優(yōu)點和缺點,以便后文選擇結(jié)構(gòu)。緊接著是包絡放大器的功耗分析,在這一部分,我們對包絡放大器的每一個部分分別進行了分析,為后面提高效率的方法提供思路。本文首先采用了經(jīng)典的包絡放大器結(jié)構(gòu)來設計一款基于0.18μm工藝的芯片,其中線性級由一個兩級放大器構(gòu)成,主要用來提供高頻電流以及消除來自于開關(guān)的紋波電流;開關(guān)級由一個降壓型DC-DC變換器和一些控制電路以及一個片外的電感構(gòu)成,提供低頻電流(占總電流比重很大),以此來提高效率。最終版圖面積0.8mm×0.5mm。在電源電壓3.3V,10MHz LTE信號,負載8歐姆情況下,最終輸出功率為27dBm,整體效率為74%。然而,包絡放大器的效率還有較大的提高空間,接著本文重點關(guān)注提高效率的方法并提出了三種提高效率的方法。在第一種方法中,利用一個軌到軌放大器來放大差異,使控制電路變得更加“準時”,這樣開關(guān)打開和關(guān)斷變得更及時,效率也因此提高了2個百分點(76%),版圖面積卻沒有因此增加。在第二種方法中,我們發(fā)現(xiàn)當線性級的輸出級放大器的NMOS管的柵壓大于一個閾值電壓時,線性級開始吸收紋波電流,我們將這些紋波電流用一個電容存儲起來,最終將效率提高了2.3個百分點(76.3%)。在第三種方法中,提出了一種更激進的方法,當功率放大器輸出功率低于一定值時,線性級和開關(guān)級停止工作,由一個直流電流提供電流,當輸出功率較大時,所有電路模塊都參與工作。這種方法有可能極大地提高整個系統(tǒng)的效率,最終初步仿真效率超過了87%。
[Abstract]:With the further development of communication technology, wireless communication equipment will become more and more complex. The efficient use of energy can not only prolong the service life of batteries, but also greatly reduce the heat dissipation of electronic instruments and improve their reliability. At present, envelope tracking technology has become a hot research topic at home and abroad because of its simple circuit structure, easy integration and obvious effect of improving the efficiency of the system. In this paper, the envelope tracking technology is studied in detail. Several new structures for improving efficiency are given, which are of great significance for improving the efficiency of circuit systems. Firstly, several common envelop amplifier structures are introduced, and their advantages and disadvantages are compared. Then there is the analysis of the power consumption of the envelope amplifier. In this part, we analyze each part of the envelope amplifier separately, and provide some ideas for improving the efficiency of the envelope amplifier. In this paper, a novel chip based on 0.18 渭 m process is designed with classical envelope amplifier structure. The linear stage is composed of a two-stage amplifier, which is mainly used to provide high frequency current and eliminate ripple current from switch. The switching level consists of a step-down DC-DC converter, some control circuits and an off-chip inductor, which provides a low frequency current (a large proportion of the total current) to improve efficiency. The final layout area is 0.8mm 脳 0.5mm. The output power is 27dBm and the overall efficiency is 74 under the condition of power supply voltage of 3.3V / 10MHz LTE and load of 8 ohms. However, there is still much room for improvement in the efficiency of the envelop amplifier. Then, this paper focuses on the methods of improving the efficiency and proposes three methods to improve the efficiency. In the first method, a rail to rail amplifier is used to amplify the difference, making the control circuit more "punctual," so that the switch on and off becomes more timely. Efficiency has thus increased by 2 percentage points, but the size of the territory has not increased as a result. In the second method, we find that when the gate voltage of the output stage amplifier of the linear stage is greater than a threshold voltage, the linear stage begins to absorb the ripple current, and we store the ripple current with a capacitor. In the end, the efficiency was raised by 2.3 percentage points or 76.3%. In the third method, a more radical method is proposed. When the output power of the power amplifier is below a certain value, the linear and switching levels stop working, and the current is supplied by a DC current, and when the output power is high, All circuit modules work. This method can greatly improve the efficiency of the whole system, and the initial simulation efficiency exceeds 87%.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN722

【參考文獻】

相關(guān)期刊論文 前1條

1 戴宇杰;呂英杰;張小興;;納米CMOS集成電路設計技術(shù)和發(fā)展趨勢[J];微納電子技術(shù);2007年12期

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本文編號：2003197