本文選題：流水線 + 功耗可配置��； 參考：《蘇州大學(xué)》2015年碩士論文

【摘要】：以CMOS圖像采集系統(tǒng)為代表的物聯(lián)網(wǎng)技術(shù)近年來吸引了眾多國內(nèi)外研究者的目光,能夠在不同數(shù)據(jù)更新率下保持較高的線性度與能量效率是圖像采集設(shè)備的重要需求。解決這個需求的關(guān)鍵是使得該系統(tǒng)中的模數(shù)轉(zhuǎn)換器實現(xiàn)功耗可配置,并且在不同速率下優(yōu)化功耗。與此同時,芯片逐漸降低的電源電壓給包括模數(shù)轉(zhuǎn)換器在內(nèi)的模擬電路設(shè)計帶來了巨大的挑戰(zhàn)。因此,低電源電壓、高信號擺幅、高線性度的模數(shù)轉(zhuǎn)換器逐漸成為了芯片設(shè)計的難點和重點。本課題設(shè)計的流水線型模數(shù)轉(zhuǎn)換器主要在信號擺幅、線性度與功耗方面進(jìn)行了優(yōu)化,論文的主要創(chuàng)新點與改進(jìn)措施在于:1)模數(shù)轉(zhuǎn)換器使用了柵壓自舉開關(guān),有效地提升了采樣保持電路的線性度;在流水線的采樣保持級與多功能增益級中采用全差分的兩級運放,提高了信號的擺幅,并在兩級運放的輸出端使用開關(guān)電容共模負(fù)反饋電路,降低了該部分電路的功耗。2)系統(tǒng)結(jié)構(gòu)上采用每級2.5位的流水線工作方式,改善由于電容失配引入的非線性;偏置電路中加入了由串行信號控制的電流調(diào)節(jié)電路,以此來優(yōu)化由于運放工作點改變造成的線性度惡化。該流水線型模數(shù)轉(zhuǎn)換器使用的工藝庫為GSMC 0.18um RF CMOS工藝,版圖總面積約為1.982mm。目前已經(jīng)完成電路和版圖設(shè)計,仿真結(jié)果表明:信噪比和線性度均達(dá)到10位以上。
[Abstract]:The Internet of things technology, represented by CMOS image acquisition system, has attracted the attention of many researchers at home and abroad in recent years. It is an important requirement for image acquisition equipment to maintain high linearity and energy efficiency under different data update rates. The key to solve this problem is to make the ADC in the system configurable and optimize the power consumption at different rates. At the same time, the decreasing supply voltage of the chip poses a great challenge to the design of analog circuits, including analog-to-digital converters. Therefore, low power supply voltage, high signal swing, high linearity A / D converter has gradually become the key point of chip design. The pipeline A / D converter designed in this paper has been optimized in the aspects of signal swing, linearity and power consumption. The main innovation and improvement measures of this paper are: 1) A / D converter uses gate voltage bootstrap switch. The linearity of the sampling and holding circuit is improved effectively, the full differential two stage operational amplifier is adopted in the sampling and holding stage and the multifunctional gain stage of pipeline, and the amplitude of the signal is increased. The switched capacitor common-mode negative feedback circuit is used in the output of the two-stage operational amplifier, which reduces the power consumption of this part of the circuit and adopts a 2.5 bit pipelined mode per stage to improve the nonlinearity caused by the capacitance mismatch. The current regulation circuit controlled by serial signal is added to the bias circuit to optimize the linearity deterioration caused by the change of operational amplifier operating point. The pipeline A / D converter uses a GSMC 0.18um RF CMOS process with a total layout area of about 1.982mm. The circuit and layout design have been completed, and the simulation results show that the signal-to-noise ratio (SNR) and linearity are above 10 bits.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 呂霆;陳蕊;;混合電路串?dāng)_和襯底耦合噪聲的優(yōu)化分析[J];電子工藝技術(shù);2010年03期

相關(guān)博士學(xué)位論文 前1條

1 陳誠;千兆以太網(wǎng)中低電壓高速模數(shù)轉(zhuǎn)換器設(shè)計研究[D];復(fù)旦大學(xué);2005年

相關(guān)碩士學(xué)位論文 前4條

1 李光輝;用于高速流水線A/D轉(zhuǎn)換器的全差分SHA設(shè)計[D];西安電子科技大學(xué);2010年

2 何偉雄;低功耗流水線模數(shù)轉(zhuǎn)換器的研究與設(shè)計[D];電子科技大學(xué);2010年

3 李治濤;基于過零檢測器的流水線式ADC的研究[D];北京交通大學(xué);2013年

4 胡北穩(wěn);應(yīng)用于伺服系統(tǒng)的12位、40MHz Pipelined ADC設(shè)計[D];華中科技大學(xué);2013年

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本文編號：1989227