本文選題：SOC + 數(shù)字��； 參考：《湘潭大學》2017年碩士論文

【摘要】：隨著科學技術的發(fā)展,人們對居住環(huán)境有著越來越高的要求。這就導致了智能家居概念的產(chǎn)生。在智能家居中,為了解決布線不便的困難,慢慢地衍生出用中短程距離無線通信來代替原始的有線通信的解決辦法。引入無線通信技術,可以解決有線網(wǎng)絡帶來的布線困難、不易于維護的缺點,在智能家居、工業(yè)控制等領域成為研究熱點。目前的無線通信技術主要有ZigBee、WIFI、射頻無線技術、藍牙等,而射頻無線技術就是通過射頻收發(fā)一體芯片實現(xiàn)的。對于它的應用用戶不需要了解通信原理和工作機制,只需要對芯片內的寄存器加以配置就可以實現(xiàn)數(shù)據(jù)的收發(fā),使用非常簡單。與此同時,這類芯片具有開發(fā)成本低、傳輸距離較遠、越障能力強的優(yōu)點,因而射頻無線通信成為研究的熱點。當前射頻電路與SOC集成電路的結合,為射頻無線通信賦予了更多的應用場景,也更加推動了社會智能化的發(fā)展。但是這也造成了射頻通信工作模式的多樣性與復雜度。因此,射頻電路功能配置與切換的完成變得尤為重要�；诂F(xiàn)階段射頻通信的研究熱度和集成電路的飛速發(fā)展,本文對SOC芯片RF915中的控制電路采用數(shù)字集成電路的方法進行設計與實現(xiàn)。在RF915中主要由射頻前端和數(shù)字控制電路組成。數(shù)字控制電路采用SPI接口進行數(shù)據(jù)傳輸,這些數(shù)據(jù)通過譯碼一部分用來對射頻前端中的寄存器進行配置,從而使得射頻前端的工作模式和頻率范圍可通過編程進行配置和改變,增加了射頻前端的靈活性。另一部分作為DAC中的數(shù)據(jù),但由于DAC采樣的速率和SPI的速度不一致,因而在中間采用了一個SRAM的存儲器存儲SPI發(fā)送來的數(shù)據(jù),并采用FIFO環(huán)的結構向SRAM中存取數(shù)據(jù),使得數(shù)據(jù)能準確有效地被采樣。同時,這個SRAM存儲器是使用memory compiler公司的IP核,這樣就縮短了開發(fā)周期,減小了設計成本。在本文中,首先介紹SOC芯片RF915芯片的整體架構,然后在電路總線結構,電路通信接口,IP核復用技術等相關理論依據(jù)的支撐下,選擇出合適的數(shù)字控制電路的設計方案;然后通過Verilog HDL語言對該數(shù)字控制電路進行邏輯設計,再通過NC-Verilog仿真工具對設計進行功能仿真,并給出仿真波形說明。然后,在SOC ENCOUNTER工具下基于GSMC 180nm的標準單元設計模式下對該設計進行物理實現(xiàn);最后,對上述工作進行總結和展望。
[Abstract]:With the development of science and technology, people have higher and higher requirements for living environment. This led to the emergence of the concept of smart home. In smart home, in order to solve the problem of inconvenient wiring, the solution of replacing the original wired communication with short-range wireless communication is derived. The introduction of wireless communication technology can solve the difficulties of wiring caused by wired network, which is difficult to maintain. It has become a research hotspot in the fields of smart home, industrial control and so on. At present, the wireless communication technology mainly includes ZigBeeWIFI, RF wireless technology, Bluetooth and so on, and RF wireless technology is realized by RF transceiver integrated chip. For its application users do not need to understand the communication principle and working mechanism, only need to configure the register in the chip to realize the data sending and receiving, the use is very simple. At the same time, this kind of chip has the advantages of low development cost, long transmission distance and strong ability of surmounting obstacles, so RF wireless communication has become a hot research topic. At present, the combination of RF circuits and SOC integrated circuits gives more application scenarios for RF wireless communication, and promotes the development of social intelligence. However, this also leads to the diversity and complexity of RF communication modes. Therefore, the completion of RF circuit function configuration and switching becomes particularly important. Based on the research of RF communication and the rapid development of integrated circuit, this paper designs and implements the control circuit of SOC chip RF915 by digital integrated circuit. In RF915, it is mainly composed of RF front end and digital control circuit. The digital control circuit uses SPI interface for data transmission, which is used to configure the registers in the RF front-end by decoding part of the data, so that the working mode and frequency range of the RF front-end can be configured and changed by programming. The flexibility of RF front end is increased. The other part is the data in DAC, but because the sampling rate of DAC is not consistent with the speed of SPI, a memory of SRAM is used in the middle to store the data sent by SPI, and the structure of FIFO loop is used to access the data in SRAM. The data can be sampled accurately and effectively. At the same time, the SRAM memory uses memory compiler's IP core, which shortens the development cycle and reduces the design cost. In this paper, the whole architecture of SOC chip RF915 chip is introduced firstly, then the design scheme of digital control circuit is selected under the support of circuit bus structure, circuit communication interface IP core multiplexing technology and so on. Then the logic design of the digital control circuit is carried out by Verilog HDL language, and the function of the design is simulated by the NC-Verilog simulation tool, and the simulation waveform is given. Then, the physical implementation of the design is carried out in the standard cell design mode based on GSMC 180nm under the SOC ENCOUNTER tool. Finally, the above work is summarized and prospected.
【學位授予單位】：湘潭大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN47

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本文編號：1964100