本文選題：Delta-Sigma調(diào)制器 + 運(yùn)算放大器共享技術(shù)�。� 參考：《哈爾濱工業(yè)大學(xué)》2017年碩士論文

【摘要】：Delta-Sigma調(diào)制器因?yàn)榫哂懈呔�、高線性度、對(duì)電路非理想特性不敏感等優(yōu)點(diǎn),在各類半導(dǎo)體傳感器以及MEMS傳感器中的應(yīng)用越來(lái)越普遍。為了實(shí)現(xiàn)傳感器系統(tǒng)的微型化與便攜化,需要設(shè)計(jì)出小尺寸、低功耗的Delta-Sigma調(diào)制器。本文對(duì)可以應(yīng)用于傳感器接口電路的低功耗Delta-Sigma調(diào)制器進(jìn)行設(shè)計(jì)實(shí)現(xiàn)。首先是對(duì)Delta Sigma調(diào)制器低功耗設(shè)計(jì)技術(shù)的發(fā)展進(jìn)行調(diào)研,著重研究了幾種常用的Delta Sigma調(diào)制器低功耗設(shè)計(jì)技術(shù)。再將多種調(diào)制器結(jié)構(gòu)從功耗、信噪比、電路設(shè)計(jì)的復(fù)雜程度方面進(jìn)行對(duì)比,最終決定采用使用運(yùn)算放大器共享技術(shù)的單環(huán)四階一位量化Delta Sigma調(diào)制結(jié)構(gòu)進(jìn)行本文的調(diào)制器設(shè)計(jì)。這種結(jié)構(gòu)各級(jí)積分器輸入輸出擺幅較低,對(duì)電路非理想特性不敏感,適宜在低功耗設(shè)計(jì)中使用。調(diào)制器的核心模塊——四級(jí)積分器,采用的是開關(guān)電容積分器,并使用運(yùn)算放大器共享技術(shù),使積分器中的運(yùn)放不存在被“閑置”的情況,減少調(diào)制器中運(yùn)算放大器的使用個(gè)數(shù),達(dá)到了降低功耗的目的。調(diào)制器系統(tǒng)的采樣頻率為3.072MHz,過(guò)采樣率為128,信號(hào)帶寬為12kHz。采用SMIC 65nm CMOS工藝進(jìn)行Delta-Sigma調(diào)制器的版圖設(shè)計(jì),遵循自上而下-自下而上的設(shè)計(jì)原則進(jìn)行版圖設(shè)計(jì)。版圖后仿真結(jié)果表明:在輸入信號(hào)幅度為0.1V,頻率為3.3734kHz時(shí),Delta-Sigma調(diào)制器的噪底在-100dB左右,SNDR為90.2dB,功耗為503.57?W,滿足設(shè)計(jì)要求。
[Abstract]:Delta-Sigma modulator is widely used in semiconductor sensors and MEMS sensors because of its advantages of high precision, high linearity and insensitivity to the non-ideal characteristics of the circuit. In order to realize the miniaturization and portability of the sensor system, a small size and low power Delta-Sigma modulator should be designed. In this paper, a low power Delta-Sigma modulator which can be used in sensor interface circuit is designed and implemented. Firstly, the development of low power design technology of Delta Sigma modulator is investigated, and several commonly used low power design techniques of Delta Sigma modulator are emphatically studied. After comparing the power consumption, signal-to-noise ratio (SNR) and the complexity of circuit design, it is decided to design the modulator using the single-ring four-order one-bit quantization Delta Sigma modulation structure using operational amplifier sharing technology. Because of its low input and output swing, this kind of integrator is not sensitive to the non-ideal characteristics of the circuit and is suitable for use in low power consumption design. The core module of the modulator, the four-stage integrator, uses the switched capacitor integrator, and uses the operational amplifier sharing technology, so that there is no "idle" situation in the operational amplifier in the integrator. The power consumption is reduced by reducing the number of operational amplifiers in the modulator. The sampling frequency of the modulator is 3.072 MHz, the over-sampling rate is 128, and the signal bandwidth is 12kHz. The layout of Delta-Sigma modulator is designed by SMIC 65nm CMOS process, followed the principle of top-down and bottom-up design. The simulation results after layout show that when the input signal amplitude is 0.1V and the frequency is 3.3734kHz, the noise base of the Delta-Sigma modulator is about -100dB, the SNDR is 90.2 dB, and the power consumption is 503.57W, which meets the design requirements.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN761

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本文編號(hào)：1955468