本文選題：全數(shù)字鎖相環(huán) + 自適應控制��； 參考：《電子科技大學》2015年碩士論文

【摘要】：鎖相環(huán)(PLL)是一個閉環(huán)負反饋控制系統(tǒng),能夠?qū)斎胄盘柕南辔缓皖l率進行有效地跟蹤。在通信、自動化以及電力系統(tǒng)等領域,鎖相環(huán)得到了廣泛的應用。由于其優(yōu)良的性能,已經(jīng)成為各類電子系統(tǒng)中重要的、不可缺少的基本元器件。與模擬鎖相環(huán)相比,全數(shù)字鎖相環(huán)(ADPLL)具有參數(shù)穩(wěn)定、抗干擾能力強以及易于集成等特點。另外,ADPLL解決了模擬鎖相環(huán)中存在的壓控振蕩器非線性、鑒相器精度不高、各個部件易于飽和、以及高階系統(tǒng)不穩(wěn)定等難題,因此,ADPLL得到了越來越多的應用。到目前為止,全數(shù)字鎖相環(huán)的結(jié)構(gòu)和控制方式已經(jīng)是多種多樣了,而鎖定時間短、同步誤差小、跟蹤頻率范圍廣以及抗干擾能力強等是衡量一個鎖相環(huán)系統(tǒng)優(yōu)良的標準。針對傳統(tǒng)全數(shù)字鎖相環(huán)設計中因控制參數(shù)固定而導致頻率跟蹤范圍窄的問題,本文設計了一種采用自適應控制與PI控制相結(jié)合的方法實現(xiàn)的新型全數(shù)字鎖相環(huán),該鎖相環(huán)可以使環(huán)路的帶寬隨輸入信號頻率的改變而自動改變。另外,針對傳統(tǒng)數(shù)字鎖相環(huán)鎖定時間與抗干擾能力之間無法協(xié)調(diào)控制的問題,本文通過所設計的自適應控制器根據(jù)相差的大小將環(huán)路捕捉過程分為快捕區(qū)、過渡區(qū)以及慢捕區(qū),使控制參數(shù)隨這三個過程自動調(diào)節(jié),有效解決了環(huán)路鎖定時間與抗噪聲性能之間矛盾的問題。另外,當輸入信號頻率發(fā)生突變后,傳統(tǒng)的全數(shù)字鎖相環(huán)會重新開始較長的鎖定過程,本文針對這個問題,設計了一種頻率控制字預置電路,該電路可以使環(huán)路在一個周期實現(xiàn)對信號的鎖定,大大減小了鎖定時間。本文在研究環(huán)路各模塊以及分析整體數(shù)學模型的基礎上,最終,在Quartus II軟件環(huán)境下,采用自頂向下的模塊化設計思路完成了整個系統(tǒng)電路的設計,并進行了編譯、綜合和仿真,最后在可編程器件上完成硬件實測。軟件功能仿真與硬件實測結(jié)果表明:所設計的鎖相環(huán)的帶寬隨輸入信號的頻率改變而改變,同時相比傳統(tǒng)PI控制鎖相環(huán),鎖定時間較短且同步誤差較小,可用于有快速同步需求的場合。當系統(tǒng)時鐘為50MHz時,在環(huán)路分頻系數(shù)為N=64的情況下,環(huán)路的鎖定時間最慢在8個輸入信號周期,最快可在一個周期完成鎖定,環(huán)路穩(wěn)定時的同步誤差為?160ns,頻率跟蹤范圍為40Hz~390KHz,且該鎖相環(huán)電路具有結(jié)構(gòu)簡單、易于集成的特點。
[Abstract]:PLL is a closed loop negative feedback control system, which can effectively track the phase and frequency of the input signal. In the fields of communication, automation and power system, PLL has been widely used. Because of its excellent performance, it has become an important and indispensable basic component in all kinds of electronic systems. Compared with analog PLL, ADPLL has the advantages of stable parameters, strong anti-jamming ability and easy integration. In addition, ADPLL solves the problems of nonlinear voltage controlled oscillator in analog PLL, low precision of phase discriminator, easy saturation of each component, and instability of high order system, so ADPLL has been applied more and more widely. Up to now, the structure and control methods of all-digital phase-locked loop have been varied, but short locking time, small synchronization error, wide tracking frequency range and strong anti-jamming ability are the good standards for a phase-locked loop system. In order to solve the problem that the frequency tracking range is narrow due to the fixed control parameters in the design of traditional all-digital phase-locked loop, a novel all-digital phase-locked loop is designed by combining adaptive control with Pi control in this paper. The PLL can automatically change the bandwidth of the loop with the change of the input signal frequency. In addition, aiming at the problem that the locking time of traditional digital phase-locked loop can not be coordinated with the anti-jamming ability, the loop capture process is divided into fast capture area, transition region and slow capture area by the designed adaptive controller according to the size of the phase difference. The control parameters are automatically adjusted with these three processes, and the contradiction between loop locking time and anti-noise performance is effectively solved. In addition, when the input signal frequency changes, the traditional all-digital phase-locked loop will start the longer locking process again. In this paper, a frequency control word preset circuit is designed to solve this problem. The circuit enables the loop to lock the signal in one cycle, greatly reducing the locking time. On the basis of studying each module of loop and analyzing the whole mathematical model, finally, under the environment of Quartus II software, the whole system circuit is designed by using top-down modular design idea, and the whole system circuit is compiled, synthesized and simulated. Finally, the hardware measurement is completed on the programmable device. The results of software function simulation and hardware measurement show that the bandwidth of the designed PLL changes with the frequency of the input signal, and the locking time is shorter and the synchronization error is smaller than that of the traditional Pi PLL. Can be used for the need for rapid synchronization. When the system clock is 50MHz, the locking time of the loop is the slowest in 8 input signal cycles when the loop frequency division coefficient is NB64, and the lockout can be completed in one cycle as soon as possible. When the loop is stabilized, the synchronization error is 160 ns and the frequency tracking range is 40 Hz ~ 390kHz. The PLL circuit has the characteristics of simple structure and easy integration.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TP273;TN791

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本文編號：1947308