本文選題：預(yù)抑制 + 電壓基準(zhǔn)源��； 參考：《微電子學(xué)》2016年06期

【摘要】：提出了一種用于全MOS電壓基準(zhǔn)源的新穎預(yù)抑制電路。采用一個(gè)大寬長(zhǎng)比PMOS管和負(fù)反饋環(huán)路,將預(yù)抑制電壓與基準(zhǔn)電壓之差固定為一個(gè)閾值電壓。獲得的預(yù)抑制電壓用來為全MOS電壓基準(zhǔn)源供電,極大地改善了基準(zhǔn)電壓的電源調(diào)整率、溫度穩(wěn)定性和電源電壓抑制比。采用Nuvoton 0.35μm 5V標(biāo)準(zhǔn)CMOS工藝進(jìn)行仿真,整個(gè)電路的版圖尺寸為64μm×136μm。結(jié)果表明:電壓基準(zhǔn)源的輸出基準(zhǔn)電壓為1.53V;電源電壓在3.4~5.5V范圍內(nèi),線性調(diào)整率為97.8μV/V;PSRR在10 Hz處為-143.2dB,在100 Hz處為-123.3dB,在1kHz處為103.3dB;環(huán)境溫度在-45℃~125℃范圍內(nèi),平均溫度系數(shù)為8.7×10~(-6)/℃。
[Abstract]:A novel pre-suppression circuit for full MOS voltage reference is proposed. A large aspect ratio PMOS transistor and a negative feedback loop are used to fix the difference between the pre-suppression voltage and the reference voltage as a threshold voltage. The obtained pre-suppression voltage is used to supply the full MOS voltage reference source, which greatly improves the power supply adjustment rate, temperature stability and power supply voltage rejection ratio of the reference voltage. Nuvoton 0.35 渭 m 5V standard CMOS process is used to simulate the circuit. The layout size of the whole circuit is 64 渭 m 脳 136 渭 m. The results show that the output reference voltage of the voltage reference source is 1.53 V, and the linear adjustment rate is 97.8 渭 V / V / V PSRR of -143.2dB at 10 Hz, -123.3 dB at 100Hz and 103.3 dB at 1kHz, and the average temperature coefficient is 8.7 脳 10 ~ (-6) dB / 鈩，

本文編號(hào)：1942894