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  本文選題：自組織網 + 低延遲��； 參考：《電子科技大學》2015年碩士論文

【摘要】：不同于傳統(tǒng)有中心節(jié)點的基站-移動終端模式的無線網絡,無線自組織網是一種由若干個對等設備自由組成的無線網絡。由于其具有網絡結構靈活、可獨立組網、抗毀性強等優(yōu)勢,無線自組織網已成為了無線通信技術發(fā)展的重要方向之一。無線自組織網通常采用CSMA/CA或TDMA的接入方式,其端到端傳輸時延較大,不適用于如軍事通信等對時延要求較高的場合。為解決自組織網中通信節(jié)點傳輸時延較大的問題,本文在以太網接口和物理層鏈路的基礎上,設計并在FPGA上實現了一種競爭和時分多址相結合的接入和組網方式,并實現了節(jié)點間的高精度全局時間同步。全文的主要工作如下:首先,討論了現有的自組織網接入方式以及常見的時間同步算法,并根據機載自組織網的時間同步及數據傳輸應用場景,以及物理層鏈路和硬件系統(tǒng)的約束,提出了明確的低延遲自組織網的網絡層設計指標。其次,根據設計指標,分為廣播通道、數據通道、收發(fā)切換三個大模塊設計了低延遲自組織網的網絡層方案,分別用于實現節(jié)點入退網及高精度時間同步、用戶IP化業(yè)務數據傳輸及TDD信道接入控制三大功能,并給出了一種在競爭接入模式和時分多址接入模式之間靈活切換的流程。隨后,分模塊詳細討論了廣播通道、數據通道和收發(fā)切換三大模塊的FPGA實現細節(jié),包括各大模塊的總體結構框圖、各子模塊的狀態(tài)轉移、組幀與解幀的流程,以及競爭和時分多址接入模式的收發(fā)切換控制,并給出了一種通過以太網接口的UDP配置通道進行鏈路管理的方法。最后,本文對網絡層連同物理層一起的全鏈路,分為雙節(jié)點AD/DA回環(huán)和多節(jié)點無線傳輸兩個場景進行了詳細的測試。結果表明,實現后的網絡層配合物理層鏈路可以在100km范圍內實現最小4.5ms的端到端延遲,提供最大約6.4Mbps的單向傳輸帶寬,可支持各種類型的以太網數據包,并實現4ns的同步精度。本文的研究內容給出了一種基于FPGA的低延遲自組織網的解決方案,具有較強的可擴展性,為自組織網的低延遲應用提供了參考方案
[Abstract]:Unlike the traditional base-mobile terminal wireless network with central nodes, the wireless ad hoc network is a wireless network composed of several peer-to-peer devices. Due to the advantages of flexible network structure, independent networking and strong survivability, wireless ad hoc networks have become one of the important development directions of wireless communication technology. Wireless ad hoc networks usually use CSMA/CA or TDMA access mode, their end-to-end transmission delay is large, so it is not suitable for military communications. In order to solve the problem of long transmission delay of communication nodes in ad hoc networks, based on Ethernet interface and physical layer link, this paper designs and implements a competitive and time-division multiple access (TDMA) access and networking mode on FPGA. The high precision global time synchronization between nodes is realized. The main work of this paper is as follows: firstly, the existing access methods and the common time synchronization algorithms are discussed, and according to the time synchronization and data transmission scenarios of the airborne ad hoc network, As well as the constraints of physical layer link and hardware system, a clear network layer design index of low delay ad hoc network is proposed. Secondly, according to the design index, it is divided into three modules: broadcast channel, data channel and transceiver switch. The network layer scheme of low delay ad hoc network is designed, which is used to realize node entry and exit network and high precision time synchronization, respectively. User IP traffic data transmission and TDD channel access control are three main functions, and a flexible switching process between competing access mode and time division multiple access mode is given. Then, the FPGA implementation details of broadcast channel, data channel and transceiver switch are discussed in detail, including the overall structure block diagram of each module, the state transition of each sub-module, the process of framing and unframing. And the transceiver switching control of competition and time division multiple access (TDMA) mode, and a method of link management through the UDP configuration channel of Ethernet interface is presented. Finally, the whole link of network layer and physical layer is divided into two scenarios: two-node AD/DA loop and multi-node wireless transmission. The results show that the realized network layer with physical layer link can realize the end-to-end delay of the minimum 4.5ms in the range of 100km, provide the maximum one-way transmission bandwidth of about 6.4Mbps, support all kinds of Ethernet packets, and realize the synchronization accuracy of 4ns. In this paper, a solution of low delay ad hoc network based on FPGA is presented, which has strong extensibility and provides a reference scheme for low delay application of ad hoc network.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791

【參考文獻】

相關期刊論文 前1條

1 崔鶴;劉云清;盛家進;;基于FPGA的UDP/IP協(xié)議棧的研究與實現[J];長春理工大學學報(自然科學版);2014年02期

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本文編號：1926161