本文選題：通用異步收發(fā)器 + 專用集成電路�。� 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：通用異步收發(fā)器,通常稱為UART,采用串行數(shù)據(jù)總線,作為一種異步收發(fā)傳輸器,被用于異步系統(tǒng)之間的通信。該總線為雙向通信,可以實(shí)現(xiàn)全雙工數(shù)據(jù)傳輸。因其傳輸線少、傳輸距離遠(yuǎn)、可靠性高、成本低等優(yōu)點(diǎn),被廣泛應(yīng)用于計(jì)算機(jī)、工業(yè)控制等通信系統(tǒng)。新一代的計(jì)算機(jī)系統(tǒng)采用高端處理器,大大提升了數(shù)據(jù)處理速度,可以在短時(shí)間內(nèi)處理大量任務(wù)。這些處理器的工作電壓通常是3.3V、2.5V或者1.8V。因此,與CPU相連接的UART也必須隨之改進(jìn)設(shè)計(jì),以進(jìn)一步降低CPU的開銷,提升整體系統(tǒng)的性能。而實(shí)現(xiàn)高性能的UART,必須將波特率、FIFO深度、供電電壓、功耗等特性指標(biāo)考慮在內(nèi)。本文采用SMIC 0.13μm CMOS工藝,在3.3V PAD供電電壓和1.2V Core供電電壓下,基于低分辨率時(shí)鐘預(yù)比例器結(jié)構(gòu),設(shè)計(jì)了一款波特率可達(dá)5 Mbps的雙通道UART。采用低分辨率時(shí)鐘預(yù)比例器結(jié)構(gòu),利用有理數(shù)分頻來(lái)取代整數(shù)分頻,可以很大程度上擴(kuò)寬波特率的范圍,提高UART性能和傳輸精度。同時(shí),多通道設(shè)計(jì)可使多個(gè)通道同時(shí)收發(fā)數(shù)據(jù),大大提高了數(shù)據(jù)傳輸速度。為了降低CPU的開銷,本文為發(fā)送模塊和接收模塊各自設(shè)計(jì)了一個(gè)64字節(jié)大小的FIFO,在DMA操作的配合下可實(shí)現(xiàn)字符塊傳輸。同時(shí),本文設(shè)計(jì)了一種包含4級(jí)中斷的中斷模式,包括發(fā)送器中斷、接收器中斷、接收線狀態(tài)中斷、調(diào)制解調(diào)器中斷等,大大降低了CPU的訪問(wèn)次數(shù),使CPU可以處理更多的任務(wù)。為了便于調(diào)試,實(shí)現(xiàn)片內(nèi)診斷功能,本文還設(shè)計(jì)了回寫模式。此外,本文還為每個(gè)通道設(shè)計(jì)了14個(gè)內(nèi)部寄存器,通過(guò)配置寄存器實(shí)現(xiàn)UART的不同模式,可通過(guò)地址線進(jìn)行選擇。為了降低系統(tǒng)的功耗,設(shè)計(jì)中采用門控時(shí)鐘來(lái)降低時(shí)鐘信號(hào)的翻轉(zhuǎn)率,操作數(shù)分離使某一單元保持靜態(tài)等策略來(lái)降低動(dòng)態(tài)功耗。版圖設(shè)計(jì)在SMIC1P6M工藝下完成。經(jīng)驗(yàn)證,在系統(tǒng)時(shí)鐘80MHz下波特率5Mbps,靜態(tài)功耗為45.32mW,core版圖面積為0.238mm2。本文與現(xiàn)有相似功能結(jié)構(gòu)的芯片相比,在FIFO深度上有所增加,功耗和面積等指標(biāo)方面大大減小。
[Abstract]:Universal asynchronous transceiver, commonly known as UART, uses serial data bus as an asynchronous transceiver for communication between asynchronous systems. The bus is two-way communication and can realize full duplex data transmission. It is widely used in computer, industrial control and other communication systems because of its advantages of less transmission lines, long transmission distance, high reliability and low cost. The new generation of computer systems use high-end processors, greatly improving the speed of data processing, can handle a large number of tasks in a short time. The operating voltages of these processors are typically 3.3 VV 2.5 V or 1.8 V. Therefore, the UART connected with CPU must be improved to further reduce the overhead of CPU and improve the performance of the whole system. In order to achieve high performance UART, the baud rate and FIFO depth, power supply voltage and power consumption must be taken into account. Using SMIC 0.13 渭 m CMOS process, a dual-channel UART with a baud rate of up to 5 Mbps is designed under 3.3 V PAD and 1.2 V Core power supply voltages, based on the low-resolution clock preratio structure. The low resolution clock preratio structure and rational frequency division instead of integer frequency division can greatly widen the range of baud rate and improve the performance and transmission accuracy of UART. At the same time, multi-channel design can make multiple channels send and receive data simultaneously, which greatly improves the speed of data transmission. In order to reduce the overhead of CPU, this paper designs a 64-byte FIFO for the sending module and the receiving module, which can realize the character block transmission with the cooperation of the DMA operation. At the same time, this paper designs an interrupt mode with four levels of interrupt, including transmitter interrupt, receive line state interrupt, modem interrupt, etc., which greatly reduces the number of CPU access and enables CPU to handle more tasks. In order to debug easily and realize the function of in-chip diagnosis, this paper also designs the write-back mode. In addition, 14 internal registers are designed for each channel. Different modes of UART are realized by configuration registers, which can be selected by address lines. In order to reduce the power consumption of the system, the gating clock is used to reduce the clock signal turnover rate, and the separation of operands to keep a unit static to reduce the dynamic power consumption. Layout design is completed under SMIC1P6M process. It is verified that under the system clock 80MHz, the baud rate is 5Mbpsand the static power consumption is 45.32mWN core. The layout area is 0.238mm ~ 2. Compared with the existing chips with similar functional structures, the depth of FIFO is increased, and the power consumption and area are greatly reduced.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 余梅;深亞微米超大規(guī)模FPGA芯片全定制版圖設(shè)計(jì)研究[D];電子科技大學(xué);2012年

，

本文編號(hào)：1901671