本文選題：低密度奇偶校驗(yàn)碼 + 低存儲編譯碼器�。� 參考：《河北大學(xué)》2015年碩士論文

【摘要】：隨著現(xiàn)代數(shù)字通信系統(tǒng)的飛速發(fā)展,低密度奇偶校驗(yàn)碼(Low-Density Parity-Check)即LDPC碼憑借其具有逼近香農(nóng)(Shannon)極限的性能以及低復(fù)雜度的譯碼算法和高并行度的硬件實(shí)現(xiàn)架構(gòu)成為了近年來信道糾錯(cuò)編碼技術(shù)研究的重點(diǎn)。本文深入研究了基于FPGA的LDPC碼高效低存儲量編譯碼器的實(shí)現(xiàn)方法。論文的主要工作包括:研究LDP C碼的編譯碼算法及并利用Matlab仿真軟件完成校驗(yàn)矩陣的構(gòu)造,對多種編譯碼算法進(jìn)行仿真比較,最終完成高效LDPC碼編譯碼器的FPGA實(shí)現(xiàn)。本文首先介紹了LDPC碼的基本概念和國內(nèi)外發(fā)展現(xiàn)狀,并通過對LDPC碼的分類和表示方法的介紹引出LDPC碼中的一類特殊碼型——準(zhǔn)循環(huán)低密度奇偶校驗(yàn)碼(Quasi Cyclic-LDPC碼),QC-LDPC碼結(jié)合了結(jié)構(gòu)性和隨機(jī)性的特點(diǎn),在保證LDPC碼的信道性能不變的情況下,大大減小了編碼算法的復(fù)雜程度,被廣泛應(yīng)用在眾多數(shù)字通信系統(tǒng)當(dāng)中。其次,本文通過Matlab仿真,實(shí)現(xiàn)了LDPC碼校驗(yàn)矩陣的不同構(gòu)造方法,經(jīng)過多次仿真測試分析各種構(gòu)造方式的優(yōu)缺點(diǎn)。然后系統(tǒng)的分析和總結(jié)LDPC碼的編譯碼方法,對傳統(tǒng)譯碼算法和快速編碼算法進(jìn)行比較,并詳細(xì)推導(dǎo)了LDPC碼在高斯白噪聲信道下置信傳播譯碼算法的消息更新規(guī)則,以及由其演化而來的對數(shù)似然比譯碼算法和最小和譯碼算法,通過綜合分析確定快速編碼算法及最小和譯碼算法作為高效LDPC碼編譯碼器的基本設(shè)計(jì)思想。最后,本文根據(jù)快速編碼算法,選取基于IEEE 802.16e標(biāo)準(zhǔn)的校驗(yàn)矩陣,只存儲基矩陣中每個(gè)子矩陣的首地址,并通過正向反向雙向遞歸計(jì)算校驗(yàn)位。設(shè)計(jì)了一種高效低存儲的LDPC碼編碼器,節(jié)省了FPGA邏輯資源開銷并提高了編碼速度。而譯碼器的設(shè)計(jì)則根據(jù)最小和譯碼算法,變量節(jié)點(diǎn)和校驗(yàn)節(jié)點(diǎn)的更新均采用塊間并行、塊內(nèi)串行的方式進(jìn)行。該方案可有效降低譯碼器對硬件存儲空間的占用,并降低了譯碼電路的布線復(fù)雜度。
[Abstract]:With the rapid development of modern digital communication system, Low-Density Parity-Check (LDPC) codes have become the focus of research on channel error correction coding in recent years because of their performance of approaching Shannon's limit, low complexity decoding algorithm and high parallelism hardware implementation architecture. In this paper, the implementation of efficient low memory codec of LDPC code based on FPGA is studied. The main work of this paper is as follows: the coding and decoding algorithm of LDP C code is studied and the construction of check matrix is completed by using Matlab simulation software. Finally, the FPGA implementation of efficient LDPC codec is finished by comparing and simulating various encoding and decoding algorithms. In this paper, the basic concept of LDPC code and its development status at home and abroad are introduced. By introducing the classification and representation of LDPC codes, a class of special codes in LDPC codes, quasi low density parity check codes, QC-LDPC codes, are introduced. The QC-LDPC codes combine the characteristics of structure and randomness. Under the condition that the channel performance of LDPC code is invariable, the complexity of the coding algorithm is greatly reduced, and it is widely used in many digital communication systems. Secondly, through Matlab simulation, different construction methods of LDPC code check matrix are realized, and the advantages and disadvantages of various construction methods are analyzed through several simulation tests. Then the encoding and decoding methods of LDPC codes are systematically analyzed and summarized. The traditional decoding algorithms and fast coding algorithms are compared, and the message updating rules of confidence propagation decoding algorithm for LDPC codes in Gao Si white noise channel are deduced in detail. The logarithmic likelihood ratio decoding algorithm and the minimum sum decoding algorithm derived from the algorithm are analyzed. The fast coding algorithm and the minimum sum decoding algorithm are determined as the basic design ideas of the efficient LDPC codec. Finally, according to the fast coding algorithm, this paper selects the check matrix based on IEEE 802.16e standard, only stores the first address of each submatrix in the base matrix, and calculates the check bit by forward reverse bidirectional recursion. An efficient and low storage LDPC encoder is designed, which saves the FPGA logic resource overhead and improves the coding speed. On the other hand, the decoder is designed according to the minimum sum decoding algorithm. The update of variable node and check node is carried out in parallel between blocks and serial within blocks. This scheme can effectively reduce the storage space of the decoder and reduce the routing complexity of the decoding circuit.
【學(xué)位授予單位】：河北大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN911.22;TN791

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