本文選題：數(shù)模轉(zhuǎn)換器(DAC) + 電流舵　； 參考：《東南大學(xué)》2015年碩士論文

【摘要】：數(shù)模轉(zhuǎn)換器(DAC)作為數(shù)字系統(tǒng)到模擬系統(tǒng)的一個(gè)重要接口,越來(lái)越受到人們的重視。近年來(lái)通信技術(shù)尤其是無(wú)線通信技術(shù)的快速發(fā)展,對(duì)DAC轉(zhuǎn)化速率的要求也越來(lái)越高。高速DAC的性能在某種程度上成為了高速通信系統(tǒng)性能的瓶頸之一。因此研究和設(shè)計(jì)高速DAC芯片具有重要的現(xiàn)實(shí)意義。論文首先介紹了DAC的工作原理和重要指標(biāo)。接著分析了電阻型、電容型和電流舵三種類(lèi)型DAC的各自特點(diǎn)和實(shí)現(xiàn)方式。電流舵架構(gòu)由于其將電流源的電流直接輸出到負(fù)載不需要任何緩沖這一固有特性使得其在高速DAC中得到廣泛應(yīng)用�；诖�,本文詳細(xì)分析和討論了影響電流舵DAC靜態(tài)特性和動(dòng)態(tài)特性的關(guān)鍵因素。分析了電流源陣列的隨機(jī)失配項(xiàng)并定量給出了電流源尺寸的選取方案,介紹了減小系統(tǒng)失配的布局方案。推導(dǎo)了電流源阻抗與靜態(tài)特性和無(wú)雜散動(dòng)態(tài)范圍(SFDR)的定量關(guān)系并分析了共源共柵電流源的輸出阻抗隨頻率的變化趨勢(shì)。所設(shè)計(jì)的6位高速DAC基于65rnmCMOS工藝,采用高四位溫度計(jì)譯碼和低兩位二進(jìn)制加權(quán)的4+2電流舵結(jié)構(gòu)。整個(gè)電路包括模擬和數(shù)字兩大部分。模擬部分主要提供所需要的電流源。通過(guò)采用內(nèi)置的帶隙電壓基準(zhǔn)源產(chǎn)生穩(wěn)定電壓,進(jìn)而通過(guò)電壓轉(zhuǎn)電流電路和電流鏡來(lái)獲得穩(wěn)定的電流源。內(nèi)置的電流源較好地保證了精度和集成度。數(shù)字部分主要為譯碼器和為了保證各路信號(hào)同步性的譯碼前后的寄存器和鎖存器。對(duì)譯碼器的設(shè)計(jì)做了精細(xì)的考慮,通過(guò)優(yōu)化邏輯結(jié)構(gòu)以及門(mén)單元電路并在其中插入緩沖器來(lái)使得譯碼器能正確處理高速信號(hào)并將各路信號(hào)之間的延時(shí)控制在一定范圍內(nèi)。為了在轉(zhuǎn)換過(guò)程中電流源陣列始終提供穩(wěn)定的電流,譯碼后的控制信號(hào)通過(guò)調(diào)制器產(chǎn)生一個(gè)高交叉點(diǎn)的差分控制信號(hào)來(lái)控制差分開(kāi)關(guān)的斷開(kāi)與閉合。這樣使得在切換過(guò)程中差分開(kāi)關(guān)不存在同時(shí)關(guān)斷的現(xiàn)象。本設(shè)計(jì)完成了原理圖設(shè)計(jì),版圖設(shè)計(jì)和后仿真。其總面積為0.675mm×0.485mm。芯片采用1.2V單電源供電,整個(gè)功耗小于20mW。后仿真結(jié)果表明具有良好的靜態(tài)和動(dòng)態(tài)特性,其DNL,INL均小于0.05LSB。在8GHz時(shí)鐘頻率作用下,輸出信號(hào)頻率在2.7GHz內(nèi)SFDR大于34dB；在5GHz時(shí)鐘頻率作用下,整個(gè)奈奎斯特帶寬SFDR大于42dB。
[Abstract]:As an important interface between digital system and analog system, DAC is paid more and more attention. In recent years, with the rapid development of communication technology, especially wireless communication technology, the requirement of DAC conversion rate is becoming higher and higher. The performance of high-speed DAC has become one of the bottlenecks of high-speed communication system to some extent. Therefore, the research and design of high-speed DAC chip has important practical significance. This paper first introduces the working principle and important index of DAC. Then, the characteristics and implementation methods of resistive type, capacitance type and current rudder are analyzed. The current rudder architecture is widely used in high speed DAC because it outputs the current directly to the load without any buffer. Based on this, the key factors affecting the static and dynamic characteristics of the current rudder DAC are analyzed and discussed in detail. The random mismatch of the current source array is analyzed and the selection scheme of the current source size is given quantitatively. The layout scheme to reduce the system mismatch is introduced. The quantitative relationship between current source impedance and static characteristics and no stray dynamic range (SFDR) is derived and the variation trend of output impedance with frequency is analyzed. Based on the 65rnmCMOS process, the six-bit high-speed DAC is designed with a high four-bit thermometer decoding and a low-two-bit binary weighted 42 current rudder structure. The whole circuit includes two parts: analog and digital. The analog part mainly provides the needed current source. The stable voltage is generated by using the built-in bandgap voltage reference source, and then the stable current source is obtained by voltage-to-current circuit and current mirror. The built-in current source ensures the accuracy and integration. The digital part is mainly a decoder and registers and latches before and after decoding to ensure the synchronization of each signal. The design of the decoder is carefully considered. By optimizing the logic structure and the gate circuit and inserting a buffer in it, the decoder can process the high speed signal correctly and control the delay between the various signals within a certain range. In order to provide a stable current during the conversion process, the decoded control signal generates a high intersection differential control signal through the modulator to control the opening and closing of the differential switch. In this way, the differential switch does not turn off at the same time in the switching process. This design completes the schematic design, layout design and post-simulation. Its total area is 0.675mm 脳 0.485mm. The chip uses 1.2V single power supply, and the whole power consumption is less than 20mW. The simulation results show that it has good static and dynamic characteristics, and its DNL INL is less than 0.05 LSBs. Under the action of 8GHz clock frequency, the output signal frequency is greater than 34dB in 2.7GHz, and the whole Nyquist bandwidth SFDR is more than 42 dB under 5GHz clock frequency.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN792

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