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  本文選題：射頻LDMOS + Trench�。� 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：現(xiàn)代移動通信的飛速發(fā)展,對信息傳輸?shù)母哔|(zhì),高量推動了射頻LDMOS向更高的頻率和更寬的帶寬應(yīng)用,同時也給設(shè)計技術(shù)帶來了嚴(yán)峻的挑戰(zhàn)。由于國內(nèi)射頻LDMOS研發(fā)能力與國外存在不小差距,開展LDMOS的研究和設(shè)計對國防和國民經(jīng)濟(jì)有重要意義。本論文主要針對S波段射頻LDMOS器件進(jìn)行設(shè)計和建模。LDMOS器件結(jié)構(gòu)采用了單層Shield源極場板;源極有源區(qū)采用減小器件面積的Trench sinker結(jié)構(gòu)�；谠摻Y(jié)構(gòu)進(jìn)行了仿真設(shè)計與部分結(jié)構(gòu)參數(shù)的優(yōu)化。并用Cadence繪制了器件版圖,在上海華虹宏力半導(dǎo)體公司進(jìn)行流片實驗。對柵長0.4μm,柵寬140μm的器件得到飽和電流210mA/mm,擊穿電壓65V,閾值電壓1.5V,截止頻率9GHz。對柵寬1mm的器件,獲得3dB增益壓縮功率30.1dBm,最大增益20.1dB以及最大效率53.1%,功率密度達(dá)到1W/mm。最后基于測試數(shù)據(jù),采用Angelov非線性模型對柵長0.4μm,柵寬140μm的LDMOS器件進(jìn)行了模型分析。其中在直流IV模型擬合時,將擬合因子P1與漏壓Vds關(guān)聯(lián),得到了較好的擬合結(jié)果。在非線性電容模型分析中,測試的漏源電容Cds發(fā)現(xiàn)其受偏壓影響較大,因此,同時對Cds、Cgs和Cgd進(jìn)行了模型擬合。最后將建立的模型嵌入到ADS中,得到了小柵寬器件的大信號模型。本論文通過器件設(shè)計仿真,測試獲得了性能較好的RF LDMOS器件。并建立了雙柵指小柵寬器件的大信號模型,為以后對大柵寬大功率RF LDMOS器件的建模奠定了良好的基礎(chǔ)。
[Abstract]:With the rapid development of modern mobile communication, the high quality and high quantity of information transmission promote the application of RF LDMOS to higher frequency and wider bandwidth. At the same time, it also brings a severe challenge to the design technology. Because of the gap between domestic RF LDMOS R & D capability and foreign countries, the research and design of LDMOS is of great significance to national defense and national economy. In this paper, we design and model the S-band RF LDMOS devices. The single-layer Shield source polar field board is used in the device structure, and the Trench sinker structure is used to reduce the device area in the source region. Based on this structure, simulation design and optimization of some structural parameters are carried out. The device layout was plotted by Cadence, and the flow sheet experiment was carried out in Shanghai Huahong Hongli Semiconductor Company. For devices with a gate length of 0.4 渭 m and a gate width of 140 渭 m, a saturation current of 210 Ma / mm, a breakdown voltage of 65 V, a threshold voltage of 1.5 V and a cut-off frequency of 9 GHz were obtained. For the devices with wide gate width 1mm, the gain compression power of 3dB is 30.1dBm, the maximum gain 20.1dB and the maximum efficiency 53.1. The power density is up to 1W / mmm. Finally, based on the test data, the Angelov nonlinear model is used to model the LDMOS devices with a gate length of 0.4 渭 m and a gate width of 140 渭 m. When fitting DC IV model, the fitting factor P1 is correlated with leakage pressure Vds, and a good fitting result is obtained. In the analysis of nonlinear capacitance model, the measured drain source capacitance (Cds) is found to be greatly affected by bias voltage. Therefore, the model fitting of CDs CGS and Cgd is carried out at the same time. Finally, the model is embedded into ADS, and the large signal model of small gate width device is obtained. In this paper, RF LDMOS devices with good performance are obtained through device design and simulation. The large signal model of double gate finger small gate width device is established, which lays a good foundation for the modeling of large gate wide and high power RF LDMOS device in the future.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386

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相關(guān)期刊論文 前1條

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本文編號：1835998