本文選題：延遲鎖定環(huán) + 時(shí)間數(shù)字轉(zhuǎn)換電路�。� 參考：《半導(dǎo)體光電》2017年03期

【摘要】：設(shè)計(jì)了一款基于延遲鎖定環(huán)(DLL)和同步計(jì)數(shù)器結(jié)構(gòu)的10位片上時(shí)間數(shù)字轉(zhuǎn)換電路(TDC)。采用兩步層級(jí)設(shè)計(jì)方法,利用同步計(jì)數(shù)器進(jìn)行粗量化輸出6位二進(jìn)制碼,量化時(shí)鐘周期的整數(shù)倍,再利用高性能差分DLL輸出16路固定相移的時(shí)鐘信號(hào)采樣,精量化不足一個(gè)時(shí)鐘周期的部分,輸出4位溫度計(jì)碼。該結(jié)構(gòu)可以提供較好的精度、動(dòng)態(tài)范圍以及轉(zhuǎn)換速度,與傳統(tǒng)的子門延時(shí)TDC相比,該結(jié)構(gòu)TDC占用的芯片面積更少,轉(zhuǎn)換速度更高,受工藝、電壓及溫度影響更少。仿真結(jié)果表明:該TDC具有LSB 62.5ps和MSB 64ns的動(dòng)態(tài)范圍,滿足一般與時(shí)間相關(guān)的單光子計(jì)數(shù)需要。
[Abstract]:A 10-bit time-to-digital conversion circuit based on DLL) and synchronous counter is designed. In this paper, a two-step hierarchical design method is used to output 6-bit binary code by using synchronous counter, which quantizes the integer times of clock cycle, and then outputs 16-channel fixed phase-shift clock signal sampling by using high performance differential DLL. Precision quantization of less than one part of the clock cycle, output 4-bit thermometer code. The structure can provide better precision, dynamic range and conversion speed. Compared with the traditional sub-gate delay TDC, the structure TDC occupies less chip area, has higher conversion speed and is less affected by technology, voltage and temperature. The simulation results show that the TDC has the dynamic range of LSB 62.5ps and MSB 64ns, which can meet the needs of time dependent single photon counting.
【作者單位】： 天津大學(xué)仁愛(ài)學(xué)院;天津職業(yè)技術(shù)師范大學(xué)電子工程學(xué)院;天津力神電池股份有限公司;
【分類號(hào)】：TN402
，

本文編號(hào)：1833620