本文選題：FPGA + 超分辨率　； 參考：《現(xiàn)代電子技術(shù)》2017年17期

【摘要】：設(shè)計基于FPGA的圖像超分辨率雙線性插值實(shí)現(xiàn)方式,提出基于單輸入雙輸出端口RAM緩沖的二級循環(huán)調(diào)度機(jī)制,用以實(shí)現(xiàn)共享資源分配和并行流水處理。單輸入雙輸出端口的RAM實(shí)現(xiàn)讀取相鄰地址的兩個數(shù)據(jù),RAM的深度為源圖像一行的像素點(diǎn)數(shù),寬度為像素數(shù)據(jù)寬度,實(shí)現(xiàn)源數(shù)據(jù)相鄰兩行像素的存儲。根據(jù)位置分析模塊得到源圖像的位置,將源圖像的數(shù)據(jù)寫入相應(yīng)RAM中進(jìn)行加權(quán)運(yùn)算。為了提高效率使用乒乓算法,設(shè)計了4個RAM,2個RAM為一組,一組RAM在加權(quán)運(yùn)算時,另一組RAM寫入數(shù)據(jù)。該設(shè)計在Kintex-7開發(fā)板上得到驗證,實(shí)現(xiàn)圖像處理速度達(dá)到25~30 f/s,同時圖像插值后不僅細(xì)節(jié)更加清晰,從直方圖中可以看到圖像得到了均衡化。
[Abstract]:An image super-resolution bilinear interpolation scheme based on FPGA is designed, and a two-stage cyclic scheduling mechanism based on single input and double output port RAM buffer is proposed to achieve shared resource allocation and parallel pipelining. The RAM of single input and double output port can realize the storage of two adjacent rows of source data. The depth of the RAM is the pixel number of one row of the source image and the width of the width of the data is the width of the pixel data. According to the position analysis module, the location of the source image is obtained, and the data of the source image is written into the corresponding RAM for weighted operation. In order to improve the efficiency of using ping-pong algorithm, we designed four Ram, two RAM as a group, one group of RAM in the weighted operation, the other group of RAM to write data. The design is verified on the Kintex-7 development board, and the speed of image processing is up to 2530 f / s. After image interpolation, not only the details are more clear, but also the image is equalized from the histogram.
【作者單位】： 南京鐵道職業(yè)技術(shù)學(xué)院;中電科技德清華瑩電子有限公司;南京航空航天大學(xué);
【基金】：國家自然科學(xué)基金面上項目(51475240) 航空科學(xué)基金自由探索類項目(2014ZD52053) 江蘇省軌道交通控制工程技術(shù)研究開發(fā)中心開放基金(KFJ1509)
【分類號】：TN791;TP391.41

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