本文選題：Turbo乘積碼 + Chase算法�。� 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：隨著無線通信技術(shù)的迅猛發(fā)展,信息傳輸?shù)目煽啃詥栴}越來越引起人們重視,關(guān)于信道編碼技術(shù)的研究也越來越多。Turbo乘積碼作為一種編碼效率高、糾錯性能好的線性分組碼,有著巨大的研究價值和應(yīng)用潛力,近些年成為了信道編碼領(lǐng)域的研究熱點(diǎn)。然而,Turbo乘積碼傳統(tǒng)的Chase迭代譯碼算法復(fù)雜度較大,不太適合硬件實(shí)現(xiàn)。因此,如何改進(jìn)Chase迭代譯碼算法以取得譯碼性能和復(fù)雜度的合理折中成為了Turbo乘積碼的研究重心。本文圍繞Turbo乘積碼編譯碼技術(shù)展開,研究并選定了一種低復(fù)雜度譯碼算法,然后基于該算法進(jìn)行了譯碼器的硬件設(shè)計(jì)及FPGA實(shí)現(xiàn)。全文研究內(nèi)容主要包括以下方面:1.在系統(tǒng)闡述Turbo乘積碼編譯碼原理的基礎(chǔ)上,深入研究了Chase迭代譯碼算法及其改進(jìn)的低復(fù)雜度算法,并仿真分析了原始算法和改進(jìn)算法的性能差異。本文采用的低復(fù)雜度改進(jìn)Chase迭代譯碼算法在610-誤碼率下能夠獲得6.8dB以上的編碼增益。2.對本文選定的低復(fù)雜度Chase迭代譯碼算法進(jìn)行了硬件設(shè)計(jì)及FPGA實(shí)現(xiàn),并通過功能仿真對設(shè)計(jì)的譯碼器電路進(jìn)行了功能上的驗(yàn)證。在主要誤碼率區(qū)間上,功能仿真相比浮點(diǎn)仿真的碼塊編碼增益差在0.1dB以內(nèi)。3.基于Altera DE5-Net FPGA開發(fā)平臺進(jìn)一步對設(shè)計(jì)的譯碼器電路進(jìn)行了驗(yàn)證及性能分析。本文設(shè)計(jì)的Turbo乘積碼譯碼器硬件資源使用率較低,最大工作時鐘頻率為333MHz,可完成最高33Mbps速率的碼塊實(shí)時譯碼,具有最低248?s的譯碼延時。研究和實(shí)現(xiàn)表明,本文采用的Turbo乘積碼低復(fù)雜度譯碼算法及據(jù)此設(shè)計(jì)的譯碼器滿足了課題需求。
[Abstract]:With the rapid development of wireless communication technology, people pay more and more attention to the reliability of information transmission. As a linear block code with high coding efficiency and good error-correcting performance, there are more and more researches on channel coding. It has great research value and application potential. In recent years, it has become a research hotspot in the field of channel coding. However, the traditional Chase iterative decoding algorithm for turbo product codes is more complex and less suitable for hardware implementation. Therefore, how to improve the Chase iterative decoding algorithm to achieve a reasonable compromise between decoding performance and complexity has become the focus of the study of Turbo product codes. In this paper, a low complexity decoding algorithm is studied and selected around the Turbo product code encoding and decoding technology, and then the hardware design and FPGA implementation of the decoder are carried out based on the algorithm. The main contents of this paper include the following aspects: 1. 1. On the basis of systematically expounding the principle of Turbo product code encoding and decoding, the Chase iterative decoding algorithm and its improved low complexity algorithm are studied in depth, and the performance differences between the original algorithm and the improved algorithm are simulated and analyzed. In this paper, the improved Chase iterative decoding algorithm with low complexity can obtain the coding gain above 6.8dB at 610-bit error rate (BER). Hardware design and FPGA implementation of the low complexity Chase iterative decoding algorithm selected in this paper are carried out, and the functional verification of the designed decoder circuit is carried out by functional simulation. Compared with floating-point simulation, the gain difference of code block coding in the main bit error rate range is within 0.1dB. 3. Based on Altera DE5-Net FPGA development platform, the designed decoder circuit is verified and its performance is analyzed. The Turbo product decoder designed in this paper has a low utilization rate of hardware resources and a maximum working clock frequency of 333MHz. It can complete the block real-time decoding with the highest 33Mbps rate and has the lowest decoding delay of 248s. The research and implementation show that the low complexity decoding algorithm of Turbo product codes and the decoder designed in this paper meet the requirements of the subject.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN911.22;TN791

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