本文選題：40nm + 流水線模數(shù)轉(zhuǎn)換器�。� 參考：《蘭州大學(xué)》2015年碩士論文

【摘要】：Intel新一代處理器使用的是目前比較先進(jìn)的14nm工藝,而國(guó)內(nèi)芯片使用的工藝還普遍停留在0.13um、0.18um階段。相對(duì)于TI等大公司,國(guó)內(nèi)ADC芯片的水平較低,市場(chǎng)基本被國(guó)外公司壟斷,國(guó)內(nèi)芯片水平急需提升。本論文首先對(duì)流水線模數(shù)轉(zhuǎn)換器中的關(guān)鍵單元進(jìn)行了詳細(xì)的計(jì)算推導(dǎo),包括運(yùn)算放大器需求的計(jì)算以及采樣電容值的確定,并分析比較了三種結(jié)構(gòu)的采樣電路。之后,使用Matlab建模工具完成了流水線模數(shù)轉(zhuǎn)換器的建模工作,不僅使各個(gè)模塊的指標(biāo)更加明確,并且為后期研究某一特定非理想因素對(duì)整體性能的影響提供了基礎(chǔ)。本論文設(shè)計(jì)了兩種結(jié)構(gòu)的運(yùn)算放大器以適應(yīng)流水線模數(shù)轉(zhuǎn)換器對(duì)運(yùn)算放大器的不同需求。由于40nm工藝下供電電壓較低、運(yùn)算放大器增益需求較高、以及功耗等因素,運(yùn)算放大器整體采用了兩級(jí)折疊共源共柵結(jié)構(gòu),運(yùn)算放大器的后仿結(jié)果能夠達(dá)到：Gain為80.41dB, GBW為759.6MHz, PM為61.1。,功耗為7.2578mW。在非理想因素的處理方面,本論文主要研究的是電容的失配以及開關(guān)的非線性電阻兩個(gè)方面。為了減小開關(guān)的非線性電阻,設(shè)計(jì)了自舉開關(guān)替代普通開關(guān),并對(duì)比了自舉開關(guān)使用前后的效果。結(jié)合其他模塊,本論文最終在SMIC 40nm CMOS工藝下完成了12bit/60Msps流水線模數(shù)轉(zhuǎn)換器的設(shè)計(jì),單通道整體后仿結(jié)果：SNDR為68.7dB, THD為-75.1dB, SFDR為74.6dB,有效位高達(dá)11.12bit,功耗為61.9mW。
[Abstract]:The current advanced 14nm process is used in the new generation of Intel processors, while the technology used in domestic chips is still generally in the 0.13um / 0.18um stage. Compared with TI and other large companies, the level of domestic ADC chips is relatively low, the market is basically monopolized by foreign companies, and the level of domestic chips needs to be improved urgently. In this paper, the key units of pipeline A / D converter are calculated and deduced in detail, including the calculation of operational amplifier requirements and the determination of sampling capacitance, and the analysis and comparison of three kinds of sampling circuits. After that, the modeling work of pipeline A / D converter is completed by using Matlab modeling tool, which not only makes the index of each module more clear, but also provides a foundation for the later study of the influence of a particular non-ideal factor on the overall performance. In this paper, two kinds of operational amplifiers are designed to meet the different requirements of pipeline A / D converters. Because of the low supply voltage in 40nm process, high gain requirement of operational amplifier and power consumption, the operational amplifier adopts a two-stage folded common-source common-gate structure. The post-simulation results of operational amplifier can reach 80.41 dB, GBW 759.6 MHz, PM 61.1.The power consumption is 7.2578 MW. In the aspect of dealing with non-ideal factors, this thesis mainly focuses on two aspects: capacitance mismatch and switch nonlinear resistance. In order to reduce the nonlinear resistance of the switch, the bootstrap switch is designed to replace the ordinary switch, and the effect of the bootstrap switch before and after the use of the bootstrap switch is compared. Combined with other modules, the design of 12bit/60Msps pipelined A / D converter in SMIC 40nm CMOS process is completed. The simulation results of single channel are as follows: SNDR is 68.7 dB, THD is -75.1 dB, SFDR is 74.6 dB, the effective bit is 11.12 bit and the power consumption is 61.9 MW.
【學(xué)位授予單位】：蘭州大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前5條

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本文編號(hào)：1816494