本文選題：功耗均衡 + 密碼芯片　； 參考：《國防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：旁路攻擊技術(shù)對密碼芯片外部可測量的一些功耗、電磁場等旁路信息進(jìn)行分析,繞過基于計算復(fù)雜度的密碼安全問題,破解密碼芯片的密鑰。面對日益嚴(yán)峻的安全問題,對芯片防御技術(shù)的研究尤為重要。雙軌功耗均衡是一種比較高效的抗功耗攻擊方法。利用該方法實現(xiàn)的模塊,其功耗取值與輸入信號的翻轉(zhuǎn)不具有相關(guān)性,從而較好地保持了功耗均衡性。由于雙軌功耗均衡單元的結(jié)構(gòu)與普通單端標(biāo)準(zhǔn)單元存在很大差異,現(xiàn)有的商業(yè)EDA工具不直接支持面向雙軌邏輯的后端操作。為了能夠最大限度的使用現(xiàn)有成熟的自動化工具對雙軌邏輯進(jìn)行后端操作,實現(xiàn)面向雙軌單元模塊的功耗均衡性,本文研究面向功耗均衡邏輯的綜合與布局布線方法。主要工作如下:1、針對現(xiàn)有成熟的EDA工具不支持雙軌邏輯的綜合問題,提出了一種基于單元信息替換的邏輯綜合方法。在進(jìn)行邏輯綜合時,將雙軌庫文件中的信息替換到單端標(biāo)準(zhǔn)庫文件中,構(gòu)建虛擬單端庫文件。最大限度的使用現(xiàn)有成熟自動化工具實現(xiàn)雙軌邏輯的綜合。2、針對雙軌單元信號的對稱性布線問題,提出了一種基于寬線的布線方法。該方法采用自定義布線規(guī)則,使用成熟EDA工具進(jìn)行寬線單軌布線。然后對布線結(jié)果的DEF(design exchange format)文件進(jìn)行自動化腳本處理,將單軌信號線拓展為雙軌信號線。最終形成對稱的雙軌布線版圖數(shù)據(jù)。3、貫通了功耗均衡模塊,從編寫RTL級代碼、邏輯綜合到布局布線的半定制流程。提取了雙軌單元的物理庫文件與時序庫文件。構(gòu)建了邏輯綜合和布局布線所需要的虛擬單端庫。以AES算法中的power模塊為例,驗證了基于單元信息替換的綜合方法和基于寬線的雙軌布線方法的可用性。SPICE模擬結(jié)果表明:模塊在不同輸入下的電源電流波形幾乎完全重合,且抗功耗攻擊參數(shù)NED(Normalized Energy Deviation)為0.09834,達(dá)到較高的功耗均衡性。
[Abstract]:The bypass attack technology analyzes the power consumption electromagnetic field and other bypass information which can be measured outside the cipher chip bypassing the cryptographic security problem based on computational complexity and cracking the key of the cipher chip. In the face of increasingly serious security problems, the research of chip defense technology is particularly important. Dual-track power equalization is an efficient method to resist power attack. The power consumption of the module realized by this method is not related to the input signal flipping, so the balance of power consumption is well maintained. Because the structure of the dual-track power equalization unit is very different from that of the common single-ended standard cell, the existing commercial EDA tools do not directly support the back-end operation for dual-track logic. In order to maximize the use of existing mature automation tools for dual-track logic back-end operation, achieve dual-track unit module power balance, this paper studies the power equalization logic synthesis and layout routing method. The main work is as follows: 1. Aiming at the problem that the existing mature EDA tools do not support two-track logic, a logic synthesis method based on unit information replacement is proposed. In the process of logic synthesis, the information in the dual-track library file is replaced by the single-ended standard library file, and the virtual single-ended library file is constructed. In order to solve the problem of symmetrical routing of dual-track unit signals, a wideband routing method is proposed to realize the synthesis of two-track logic by using existing mature automation tools to the maximum extent. The method adopts custom routing rules and uses mature EDA tools for wide line monorail routing. Then, the DEF(design exchange format file of the routing result is processed automatically, and the monorail signal line is extended to double track signal line. Finally, the symmetrical double-track layout data. 3 is formed, and the power balance module is passed through. From writing the RTL level code, the logic synthesizes to the semi-custom flow of layout and routing. The physical library file and timing database file of dual track unit are extracted. The virtual single end library for logic synthesis and layout and routing is constructed. Taking the power module in the AES algorithm as an example, the availability of the synthesis method based on unit information replacement and the two-track routing method based on wide wire are verified. The simulation results show that the power current waveform of the module is almost completely overlapped under different input conditions. The anti-power attack parameter NED(Normalized Energy selection is 0.09834, which achieves high power equalization.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN405

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本文編號：1804765