本文選題：DDS + PLL�。� 參考：《上海師范大學(xué)》2015年碩士論文

【摘要】：接收機(jī)系統(tǒng)頻率合成器的主要功能是給接收機(jī)綜合基帶子系統(tǒng)和接收機(jī)射頻子系統(tǒng)提供所需的時(shí)鐘信號(hào)和本振信號(hào),頻率合成器是現(xiàn)代電子系統(tǒng)的重要組成部分,是決定電子系統(tǒng)性能的關(guān)鍵設(shè)備之一。隨著現(xiàn)代通信技術(shù)的發(fā)展,系統(tǒng)對(duì)頻率合成器提出了越來越多的要求。低相位噪聲、高頻譜純度、高捷變速率和高頻率分辨率的頻率合成器己經(jīng)成為頻率合成技術(shù)發(fā)展的主要趨勢(shì)。本課題采用DDS與PLL相結(jié)合的混合頻率合成技術(shù)實(shí)現(xiàn)頻率合成器,DDS提供PLL的參考輸入信號(hào),PLL中的鑒相器芯片內(nèi)集成有數(shù)字可編程的預(yù)分頻器和分頻器,該結(jié)構(gòu)綜合了DDS和PLL兩者的優(yōu)點(diǎn),同時(shí)又在很大程度上克服兩者的缺點(diǎn),很好地滿足了課題的設(shè)計(jì)需要。本文首先講述了頻率合成技術(shù)的概念,回顧了頻率合成技術(shù)的發(fā)展歷程,介紹了在頻率合成技術(shù)上,國(guó)內(nèi)外的發(fā)展現(xiàn)狀。然后介紹了DDS與PLL的概念、結(jié)構(gòu)、工作原理等,分析了相位噪聲和雜散的主要來源。接著依據(jù)課題指標(biāo)要求,確定設(shè)計(jì)方案和幾個(gè)核心芯片,分析方案可行性,并詳細(xì)講述了DDS電路及鎖相環(huán)電路的設(shè)計(jì)方法,以及PCB制板的規(guī)則和電磁兼容性設(shè)計(jì)。最后對(duì)頻率合成器的幾個(gè)主要性能指標(biāo)的進(jìn)行了測(cè)試。最終的測(cè)試結(jié)果顯示,在41.4MHz-71.4MHz的頻率范圍內(nèi),頻率步進(jìn)為1Hz,相位噪聲優(yōu)于-127d Bc/Hz(±20KHz),雜散優(yōu)于-55d B,跳頻時(shí)間≤3ms(1Hz頻差),達(dá)到了課題性能指標(biāo)的要求。
[Abstract]:The main function of the frequency synthesizer of the receiver system is to provide the needed clock signal and local oscillator signal to the receiver integrated baseband subsystem and the receiver radio frequency subsystem. The frequency synthesizer is an important part of the modern electronic system. It is one of the key equipments that determine the performance of electronic system. With the development of modern communication technology, frequency synthesizer is required more and more. Frequency synthesizers with low phase noise, high spectral purity, high agility rate and high frequency resolution have become the main trend of frequency synthesis technology. In this paper, a hybrid frequency synthesizer technique, which combines DDS and PLL, is used to realize the integration of digital programmable predivider and frequency divider in the phase discriminator chip of the frequency synthesizer DDS which provides the reference input signal of PLL. The structure combines the advantages of both DDS and PLL, and at the same time overcomes the shortcomings of both to a great extent, and meets the design needs of the subject well. This paper first describes the concept of frequency synthesis technology, reviews the development of frequency synthesis technology, and introduces the development of frequency synthesis technology at home and abroad. Then, the concept, structure and working principle of DDS and PLL are introduced, and the main sources of phase noise and stray are analyzed. Then according to the requirements of the project, the design scheme and several core chips are determined, and the feasibility of the scheme is analyzed. The design method of DDS circuit and PLL circuit, as well as the rules of PCB board making and the design of EMC are described in detail. Finally, several main performance indexes of the frequency synthesizer are tested. The final test results show that in the frequency range of 41.4MHz-71.4MHz, the frequency step is 1 Hz, the phase noise is better than -127 d Bc / Hz (鹵20 KHz), the spurious is better than -55 dB, and the frequency hopping time is 鈮，

本文編號(hào)：1800106